diff --git a/project.py b/project.py
index f1c92df..fa78f88 100644
--- a/project.py
+++ b/project.py
@@ -120,7 +120,7 @@ class Project():
             self.src_files              = self.get_hdl_source()
             self.top_verilog_filename   = self.find_top_verilog()
         else:
-            self.top_module             = f"user_module_{self.wokwi_id}"
+            self.top_module             = f"tt_um_wokwi_{self.wokwi_id}"
             self.src_files              = self.get_wokwi_source()
             self.top_verilog_filename   = self.src_files[0]
 
@@ -128,7 +128,7 @@ class Project():
         self.scanchain_instance     = f"scanchain_{self.index :03}"
 
     def get_wokwi_source(self):
-        src_file = "user_module_{}.v".format(self.wokwi_id)
+        src_file = "tt_um_wokwi_{}.v".format(self.wokwi_id)
         return [src_file, 'cells.v']
 
     def get_hdl_source(self):
diff --git a/testing/src-tpl/Makefile b/testing/src-tpl/Makefile
index 96e31df..ee6001a 100644
--- a/testing/src-tpl/Makefile
+++ b/testing/src-tpl/Makefile
@@ -9,7 +9,7 @@ TOPLEVEL_LANG ?= verilog
 ifneq ($(GATES),yes)
 
 # this is the only part you should need to modify:
-VERILOG_SOURCES += $(PWD)/cells.v  $(PWD)/user_module_WOKWI_ID.v $(PWD)/test_wokwi.v
+VERILOG_SOURCES += $(PWD)/cells.v  $(PWD)/tt_um_wokwi_WOKWI_ID.v $(PWD)/test_wokwi.v
 
 
 else
diff --git a/testing/src-tpl/test_wokwi.v b/testing/src-tpl/test_wokwi.v
index 0077464..564f9be 100644
--- a/testing/src-tpl/test_wokwi.v
+++ b/testing/src-tpl/test_wokwi.v
@@ -6,7 +6,7 @@ module test_wokwi ();
   wire [7:0] io_out;
   wire [7:0] io_in;
 
-  user_module_WOKWI_ID dut (
+  tt_um_wokwi_WOKWI_ID dut (
   `ifdef GL_TEST
       .vccd1( 1'b1),
       .vssd1( 1'b0),