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style(rom): format verilog code with verible

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This commit is contained in:
Uri Shaked
2025-03-30 12:15:44 +03:00
parent d04d1cbd11
commit 0a5eadaf88
1 changed files with 17 additions and 17 deletions
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rom/tt_um_chip_rom.v
+3 -3
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@@ -10,21 +10,21 @@
`default_nettype none `default_nettype none
`ifndef ROM_VMEM_PATH `ifndef ROM_VMEM_PATH
`define ROM_VMEM_PATH "rom.vmem" `define ROM_VMEM_PATH "rom.vmem"
`endif `endif
module tt_um_chip_rom ( module tt_um_chip_rom (
input wire [7:0] ui_in, // Dedicated inputs input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out,// IOs: Output path output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, input wire ena,
input wire clk, input wire clk,
input wire rst_n input wire rst_n
); );
reg [7:0] rom_data [0:255]; reg [7:0] rom_data[0:255];
initial begin initial begin
$readmemh(`ROM_VMEM_PATH, rom_data); $readmemh(`ROM_VMEM_PATH, rom_data);