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feat(fpga): read seed / target frequency from environment

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Read the values from TT_FPGA_SEED / TT_FPGA_FREQ, and default to 12 MHz frequency.
This commit is contained in:
Uri Shaked
2024-05-01 23:47:35 +03:00
parent b6ec741349
commit 0c171af9b4
1 changed files with 4 additions and 1 deletions
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project.py
+4 -1
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@@ -530,7 +530,10 @@ class Project:
logging.error("synthesis failed") logging.error("synthesis failed")
exit(1) exit(1)
nextpnr_cmd = f"nextpnr-ice40 -l {build_dir}/02-nextpnr.log --pcf-allow-unconstrained --seed 10 --freq 48 --package sg48 --up5k --asc {build_dir}/tt_fpga.asc --pcf {SCRIPT_DIR}/fpga/tt_fpga_top.pcf --json {build_dir}/tt_fpga.json" seed = os.getenv("TT_FPGA_SEED", "10")
freq = os.getenv("TT_FPGA_FREQ", "12")
nextpnr_cmd = f"nextpnr-ice40 -l {build_dir}/02-nextpnr.log --pcf-allow-unconstrained --seed {seed} --freq {freq} --package sg48 --up5k --asc {build_dir}/tt_fpga.asc --pcf {SCRIPT_DIR}/fpga/tt_fpga_top.pcf --json {build_dir}/tt_fpga.json"
logging.debug(nextpnr_cmd) logging.debug(nextpnr_cmd)
p = subprocess.run(nextpnr_cmd, shell=True) p = subprocess.run(nextpnr_cmd, shell=True)
if p.returncode != 0: if p.returncode != 0: