From ad17dca51b4c1bc3fcab36d599a036b9d921f4aa Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Sun, 31 May 2026 13:56:43 +0300 Subject: [PATCH 1/3] feat(tech/gf180mcuD): analog def files + magic init script --- .../def/analog/magic_init_project.tcl | 54 +++ tech/gf180mcuD/def/analog/tt_analog_1x2.def | 363 ++++++++++++++++++ .../def/analog/tt_analog_1x2_pgvaa.def | 363 ++++++++++++++++++ tech/gf180mcuD/def/analog/tt_analog_2x2.def | 363 ++++++++++++++++++ .../def/analog/tt_analog_2x2_pgvaa.def | 363 ++++++++++++++++++ tech/gf180mcuD/def/analog/tt_analog_3x2.def | 363 ++++++++++++++++++ .../def/analog/tt_analog_3x2_pgvaa.def | 363 ++++++++++++++++++ tech/gf180mcuD/def/analog/tt_analog_4x2.def | 363 ++++++++++++++++++ .../def/analog/tt_analog_4x2_pgvaa.def | 363 ++++++++++++++++++ 9 files changed, 2958 insertions(+) create mode 100644 tech/gf180mcuD/def/analog/magic_init_project.tcl create mode 100644 tech/gf180mcuD/def/analog/tt_analog_1x2.def create mode 100644 tech/gf180mcuD/def/analog/tt_analog_1x2_pgvaa.def create mode 100644 tech/gf180mcuD/def/analog/tt_analog_2x2.def create mode 100644 tech/gf180mcuD/def/analog/tt_analog_2x2_pgvaa.def create mode 100644 tech/gf180mcuD/def/analog/tt_analog_3x2.def create mode 100644 tech/gf180mcuD/def/analog/tt_analog_3x2_pgvaa.def create mode 100644 tech/gf180mcuD/def/analog/tt_analog_4x2.def create mode 100644 tech/gf180mcuD/def/analog/tt_analog_4x2_pgvaa.def diff --git a/tech/gf180mcuD/def/analog/magic_init_project.tcl b/tech/gf180mcuD/def/analog/magic_init_project.tcl new file mode 100644 index 0000000..a228856 --- /dev/null +++ b/tech/gf180mcuD/def/analog/magic_init_project.tcl @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024-2026 Tiny Tapeout LTD +# Author: Uri Shaked +# Description: This script initializes a new Magic project for an analog design on Tiny Tapeout. + +# Important: before running this script, download the the .def file from +# https://raw.githubusercontent.com/TinyTapeout/tt-support-tools/main/tech/gf180mcuD/def/analog/tt_analog_1x2.def + +# Change the settings below to match your design: +# ------------------------------------------------ +set TOP_LEVEL_CELL tt_um_analog_example +set TEMPLATE_FILE tt_analog_1x2.def +set POWER_STRIPE_WIDTH 2um ;# The minimum width is 0.8um + +# Power stripes: NET name, x position. You can add additional power stripes for each net, as needed. +set POWER_STRIPES { + VDPWR 1um + VGND 4um +} +# If you use the pgvaa (second supply) template, uncomment the line below: +#lappend POWER_STRIPES VAPWR 7um + +# Read in the pin positions +# ------------------------- +def read $TEMPLATE_FILE +cellname rename tt_um_template $TOP_LEVEL_CELL + +# Draw the power stripes +# -------------------------------- +proc draw_power_stripe {name x} { + global POWER_STRIPE_WIDTH + box $x 5um $x 320.36um + box width $POWER_STRIPE_WIDTH + paint metal4 + label $name FreeSans 0.25u -metal4 + port make + port use [expr {$name eq "VGND" ? "ground" : "power"}] + port class bidirectional + port connections n s e w +} + +# You can extra power stripes, as you need. +foreach {name x} $POWER_STRIPES { + puts "Drawing power stripe $name at $x" + draw_power_stripe $name $x +} + +# Save the layout and export GDS/LEF +# ---------------------------------- +save ${TOP_LEVEL_CELL}.mag +file mkdir gds +gds write gds/${TOP_LEVEL_CELL}.gds +file mkdir lef +lef write lef/${TOP_LEVEL_CELL}.lef -hide -pinonly diff --git a/tech/gf180mcuD/def/analog/tt_analog_1x2.def b/tech/gf180mcuD/def/analog/tt_analog_1x2.def new file mode 100644 index 0000000..d087d89 --- /dev/null +++ b/tech/gf180mcuD/def/analog/tt_analog_1x2.def @@ -0,0 +1,363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 693280 650720 ) ; +ROW ROW_0 GF018hv5v_mcu_sc7 6720 7840 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_1 GF018hv5v_mcu_sc7 6720 15680 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_2 GF018hv5v_mcu_sc7 6720 23520 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_3 GF018hv5v_mcu_sc7 6720 31360 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_4 GF018hv5v_mcu_sc7 6720 39200 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_5 GF018hv5v_mcu_sc7 6720 47040 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_6 GF018hv5v_mcu_sc7 6720 54880 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_7 GF018hv5v_mcu_sc7 6720 62720 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_8 GF018hv5v_mcu_sc7 6720 70560 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_9 GF018hv5v_mcu_sc7 6720 78400 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_10 GF018hv5v_mcu_sc7 6720 86240 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_11 GF018hv5v_mcu_sc7 6720 94080 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_12 GF018hv5v_mcu_sc7 6720 101920 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_13 GF018hv5v_mcu_sc7 6720 109760 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_14 GF018hv5v_mcu_sc7 6720 117600 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_15 GF018hv5v_mcu_sc7 6720 125440 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_16 GF018hv5v_mcu_sc7 6720 133280 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_17 GF018hv5v_mcu_sc7 6720 141120 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_18 GF018hv5v_mcu_sc7 6720 148960 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_19 GF018hv5v_mcu_sc7 6720 156800 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_20 GF018hv5v_mcu_sc7 6720 164640 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_21 GF018hv5v_mcu_sc7 6720 172480 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_22 GF018hv5v_mcu_sc7 6720 180320 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_23 GF018hv5v_mcu_sc7 6720 188160 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_24 GF018hv5v_mcu_sc7 6720 196000 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_25 GF018hv5v_mcu_sc7 6720 203840 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_26 GF018hv5v_mcu_sc7 6720 211680 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_27 GF018hv5v_mcu_sc7 6720 219520 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_28 GF018hv5v_mcu_sc7 6720 227360 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_29 GF018hv5v_mcu_sc7 6720 235200 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_30 GF018hv5v_mcu_sc7 6720 243040 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_31 GF018hv5v_mcu_sc7 6720 250880 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_32 GF018hv5v_mcu_sc7 6720 258720 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_33 GF018hv5v_mcu_sc7 6720 266560 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_34 GF018hv5v_mcu_sc7 6720 274400 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_35 GF018hv5v_mcu_sc7 6720 282240 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_36 GF018hv5v_mcu_sc7 6720 290080 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_37 GF018hv5v_mcu_sc7 6720 297920 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_38 GF018hv5v_mcu_sc7 6720 305760 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_39 GF018hv5v_mcu_sc7 6720 313600 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_40 GF018hv5v_mcu_sc7 6720 321440 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_41 GF018hv5v_mcu_sc7 6720 329280 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_42 GF018hv5v_mcu_sc7 6720 337120 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_43 GF018hv5v_mcu_sc7 6720 344960 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_44 GF018hv5v_mcu_sc7 6720 352800 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_45 GF018hv5v_mcu_sc7 6720 360640 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_46 GF018hv5v_mcu_sc7 6720 368480 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_47 GF018hv5v_mcu_sc7 6720 376320 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_48 GF018hv5v_mcu_sc7 6720 384160 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_49 GF018hv5v_mcu_sc7 6720 392000 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_50 GF018hv5v_mcu_sc7 6720 399840 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_51 GF018hv5v_mcu_sc7 6720 407680 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_52 GF018hv5v_mcu_sc7 6720 415520 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_53 GF018hv5v_mcu_sc7 6720 423360 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_54 GF018hv5v_mcu_sc7 6720 431200 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_55 GF018hv5v_mcu_sc7 6720 439040 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_56 GF018hv5v_mcu_sc7 6720 446880 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_57 GF018hv5v_mcu_sc7 6720 454720 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_58 GF018hv5v_mcu_sc7 6720 462560 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_59 GF018hv5v_mcu_sc7 6720 470400 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_60 GF018hv5v_mcu_sc7 6720 478240 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_61 GF018hv5v_mcu_sc7 6720 486080 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_62 GF018hv5v_mcu_sc7 6720 493920 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_63 GF018hv5v_mcu_sc7 6720 501760 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_64 GF018hv5v_mcu_sc7 6720 509600 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_65 GF018hv5v_mcu_sc7 6720 517440 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_66 GF018hv5v_mcu_sc7 6720 525280 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_67 GF018hv5v_mcu_sc7 6720 533120 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_68 GF018hv5v_mcu_sc7 6720 540960 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_69 GF018hv5v_mcu_sc7 6720 548800 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_70 GF018hv5v_mcu_sc7 6720 556640 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_71 GF018hv5v_mcu_sc7 6720 564480 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_72 GF018hv5v_mcu_sc7 6720 572320 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_73 GF018hv5v_mcu_sc7 6720 580160 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_74 GF018hv5v_mcu_sc7 6720 588000 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_75 GF018hv5v_mcu_sc7 6720 595840 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_76 GF018hv5v_mcu_sc7 6720 603680 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_77 GF018hv5v_mcu_sc7 6720 611520 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_78 GF018hv5v_mcu_sc7 6720 619360 N DO 607 BY 1 STEP 1120 0 ; +ROW ROW_79 GF018hv5v_mcu_sc7 6720 627200 FS DO 607 BY 1 STEP 1120 0 ; +ROW ROW_80 GF018hv5v_mcu_sc7 6720 635040 N DO 607 BY 1 STEP 1120 0 ; +TRACKS X 560 DO 619 STEP 1120 LAYER Metal1 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal1 ; +TRACKS X 560 DO 619 STEP 1120 LAYER Metal2 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal2 ; +TRACKS X 560 DO 619 STEP 1120 LAYER Metal3 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal3 ; +TRACKS X 560 DO 619 STEP 1120 LAYER Metal4 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal4 ; +TRACKS X 900 DO 385 STEP 1800 LAYER Metal5 ; +TRACKS Y 900 DO 361 STEP 1800 LAYER Metal5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 51 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 662480 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 677040 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 647920 649720 ) N ; + - ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 654640 1000 ) N ; + - ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 567280 1000 ) N ; + - ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 479920 1000 ) N ; + - ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 392560 1000 ) N ; + - ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 305200 1000 ) N ; + - ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 217840 1000 ) N ; + - ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 130480 1000 ) N ; + - ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 43120 1000 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 633360 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 618800 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 604240 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 589680 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 575120 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 560560 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 546000 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 531440 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 516880 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 502320 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 487760 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 473200 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 458640 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 444080 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 429520 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 414960 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 167440 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 152880 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 138320 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 123760 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 109200 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 94640 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 80080 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 65520 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 283920 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 269360 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 254800 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 240240 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 225680 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 211120 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 196560 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 182000 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 400400 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 385840 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 371280 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 356720 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 342160 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 327600 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 313040 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 298480 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VPWR + USE POWER ; + - VGND + USE GROUND ; +END SPECIALNETS +NETS 51 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ua[0] ( PIN ua[0] ) + USE SIGNAL ; + - ua[1] ( PIN ua[1] ) + USE SIGNAL ; + - ua[2] ( PIN ua[2] ) + USE SIGNAL ; + - ua[3] ( PIN ua[3] ) + USE SIGNAL ; + - ua[4] ( PIN ua[4] ) + USE SIGNAL ; + - ua[5] ( PIN ua[5] ) + USE SIGNAL ; + - ua[6] ( PIN ua[6] ) + USE SIGNAL ; + - ua[7] ( PIN ua[7] ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/analog/tt_analog_1x2_pgvaa.def b/tech/gf180mcuD/def/analog/tt_analog_1x2_pgvaa.def new file mode 100644 index 0000000..3f91b4a --- /dev/null +++ b/tech/gf180mcuD/def/analog/tt_analog_1x2_pgvaa.def @@ -0,0 +1,363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 657440 650720 ) ; +ROW ROW_0 GF018hv5v_mcu_sc7 6720 7840 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_1 GF018hv5v_mcu_sc7 6720 15680 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_2 GF018hv5v_mcu_sc7 6720 23520 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_3 GF018hv5v_mcu_sc7 6720 31360 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_4 GF018hv5v_mcu_sc7 6720 39200 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_5 GF018hv5v_mcu_sc7 6720 47040 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_6 GF018hv5v_mcu_sc7 6720 54880 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_7 GF018hv5v_mcu_sc7 6720 62720 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_8 GF018hv5v_mcu_sc7 6720 70560 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_9 GF018hv5v_mcu_sc7 6720 78400 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_10 GF018hv5v_mcu_sc7 6720 86240 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_11 GF018hv5v_mcu_sc7 6720 94080 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_12 GF018hv5v_mcu_sc7 6720 101920 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_13 GF018hv5v_mcu_sc7 6720 109760 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_14 GF018hv5v_mcu_sc7 6720 117600 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_15 GF018hv5v_mcu_sc7 6720 125440 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_16 GF018hv5v_mcu_sc7 6720 133280 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_17 GF018hv5v_mcu_sc7 6720 141120 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_18 GF018hv5v_mcu_sc7 6720 148960 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_19 GF018hv5v_mcu_sc7 6720 156800 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_20 GF018hv5v_mcu_sc7 6720 164640 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_21 GF018hv5v_mcu_sc7 6720 172480 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_22 GF018hv5v_mcu_sc7 6720 180320 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_23 GF018hv5v_mcu_sc7 6720 188160 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_24 GF018hv5v_mcu_sc7 6720 196000 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_25 GF018hv5v_mcu_sc7 6720 203840 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_26 GF018hv5v_mcu_sc7 6720 211680 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_27 GF018hv5v_mcu_sc7 6720 219520 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_28 GF018hv5v_mcu_sc7 6720 227360 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_29 GF018hv5v_mcu_sc7 6720 235200 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_30 GF018hv5v_mcu_sc7 6720 243040 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_31 GF018hv5v_mcu_sc7 6720 250880 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_32 GF018hv5v_mcu_sc7 6720 258720 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_33 GF018hv5v_mcu_sc7 6720 266560 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_34 GF018hv5v_mcu_sc7 6720 274400 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_35 GF018hv5v_mcu_sc7 6720 282240 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_36 GF018hv5v_mcu_sc7 6720 290080 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_37 GF018hv5v_mcu_sc7 6720 297920 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_38 GF018hv5v_mcu_sc7 6720 305760 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_39 GF018hv5v_mcu_sc7 6720 313600 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_40 GF018hv5v_mcu_sc7 6720 321440 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_41 GF018hv5v_mcu_sc7 6720 329280 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_42 GF018hv5v_mcu_sc7 6720 337120 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_43 GF018hv5v_mcu_sc7 6720 344960 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_44 GF018hv5v_mcu_sc7 6720 352800 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_45 GF018hv5v_mcu_sc7 6720 360640 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_46 GF018hv5v_mcu_sc7 6720 368480 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_47 GF018hv5v_mcu_sc7 6720 376320 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_48 GF018hv5v_mcu_sc7 6720 384160 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_49 GF018hv5v_mcu_sc7 6720 392000 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_50 GF018hv5v_mcu_sc7 6720 399840 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_51 GF018hv5v_mcu_sc7 6720 407680 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_52 GF018hv5v_mcu_sc7 6720 415520 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_53 GF018hv5v_mcu_sc7 6720 423360 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_54 GF018hv5v_mcu_sc7 6720 431200 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_55 GF018hv5v_mcu_sc7 6720 439040 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_56 GF018hv5v_mcu_sc7 6720 446880 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_57 GF018hv5v_mcu_sc7 6720 454720 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_58 GF018hv5v_mcu_sc7 6720 462560 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_59 GF018hv5v_mcu_sc7 6720 470400 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_60 GF018hv5v_mcu_sc7 6720 478240 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_61 GF018hv5v_mcu_sc7 6720 486080 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_62 GF018hv5v_mcu_sc7 6720 493920 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_63 GF018hv5v_mcu_sc7 6720 501760 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_64 GF018hv5v_mcu_sc7 6720 509600 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_65 GF018hv5v_mcu_sc7 6720 517440 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_66 GF018hv5v_mcu_sc7 6720 525280 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_67 GF018hv5v_mcu_sc7 6720 533120 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_68 GF018hv5v_mcu_sc7 6720 540960 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_69 GF018hv5v_mcu_sc7 6720 548800 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_70 GF018hv5v_mcu_sc7 6720 556640 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_71 GF018hv5v_mcu_sc7 6720 564480 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_72 GF018hv5v_mcu_sc7 6720 572320 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_73 GF018hv5v_mcu_sc7 6720 580160 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_74 GF018hv5v_mcu_sc7 6720 588000 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_75 GF018hv5v_mcu_sc7 6720 595840 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_76 GF018hv5v_mcu_sc7 6720 603680 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_77 GF018hv5v_mcu_sc7 6720 611520 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_78 GF018hv5v_mcu_sc7 6720 619360 N DO 575 BY 1 STEP 1120 0 ; +ROW ROW_79 GF018hv5v_mcu_sc7 6720 627200 FS DO 575 BY 1 STEP 1120 0 ; +ROW ROW_80 GF018hv5v_mcu_sc7 6720 635040 N DO 575 BY 1 STEP 1120 0 ; +TRACKS X 560 DO 587 STEP 1120 LAYER Metal1 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal1 ; +TRACKS X 560 DO 587 STEP 1120 LAYER Metal2 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal2 ; +TRACKS X 560 DO 587 STEP 1120 LAYER Metal3 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal3 ; +TRACKS X 560 DO 587 STEP 1120 LAYER Metal4 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal4 ; +TRACKS X 900 DO 365 STEP 1800 LAYER Metal5 ; +TRACKS Y 900 DO 361 STEP 1800 LAYER Metal5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 51 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626640 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 641200 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 612080 649720 ) N ; + - ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 618800 1000 ) N ; + - ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 531440 1000 ) N ; + - ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 444080 1000 ) N ; + - ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 356720 1000 ) N ; + - ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 269360 1000 ) N ; + - ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 182000 1000 ) N ; + - ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 94640 1000 ) N ; + - ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 7280 1000 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 597520 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582960 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 568400 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553840 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 539280 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524720 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 510160 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495600 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 481040 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 466480 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451920 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 437360 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422800 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 408240 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393680 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 379120 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131600 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 117040 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 102480 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87920 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 73360 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58800 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 44240 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29680 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 248080 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 233520 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218960 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 204400 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189840 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 175280 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160720 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 146160 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364560 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 350000 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 335440 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320880 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 306320 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291760 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 277200 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262640 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VPWR + USE POWER ; + - VGND + USE GROUND ; +END SPECIALNETS +NETS 51 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ua[0] ( PIN ua[0] ) + USE SIGNAL ; + - ua[1] ( PIN ua[1] ) + USE SIGNAL ; + - ua[2] ( PIN ua[2] ) + USE SIGNAL ; + - ua[3] ( PIN ua[3] ) + USE SIGNAL ; + - ua[4] ( PIN ua[4] ) + USE SIGNAL ; + - ua[5] ( PIN ua[5] ) + USE SIGNAL ; + - ua[6] ( PIN ua[6] ) + USE SIGNAL ; + - ua[7] ( PIN ua[7] ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/analog/tt_analog_2x2.def b/tech/gf180mcuD/def/analog/tt_analog_2x2.def new file mode 100644 index 0000000..eecf8cf --- /dev/null +++ b/tech/gf180mcuD/def/analog/tt_analog_2x2.def @@ -0,0 +1,363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 1422400 650720 ) ; +ROW ROW_0 GF018hv5v_mcu_sc7 6720 7840 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_1 GF018hv5v_mcu_sc7 6720 15680 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_2 GF018hv5v_mcu_sc7 6720 23520 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_3 GF018hv5v_mcu_sc7 6720 31360 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_4 GF018hv5v_mcu_sc7 6720 39200 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_5 GF018hv5v_mcu_sc7 6720 47040 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_6 GF018hv5v_mcu_sc7 6720 54880 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_7 GF018hv5v_mcu_sc7 6720 62720 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_8 GF018hv5v_mcu_sc7 6720 70560 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_9 GF018hv5v_mcu_sc7 6720 78400 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_10 GF018hv5v_mcu_sc7 6720 86240 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_11 GF018hv5v_mcu_sc7 6720 94080 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_12 GF018hv5v_mcu_sc7 6720 101920 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_13 GF018hv5v_mcu_sc7 6720 109760 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_14 GF018hv5v_mcu_sc7 6720 117600 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_15 GF018hv5v_mcu_sc7 6720 125440 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_16 GF018hv5v_mcu_sc7 6720 133280 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_17 GF018hv5v_mcu_sc7 6720 141120 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_18 GF018hv5v_mcu_sc7 6720 148960 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_19 GF018hv5v_mcu_sc7 6720 156800 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_20 GF018hv5v_mcu_sc7 6720 164640 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_21 GF018hv5v_mcu_sc7 6720 172480 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_22 GF018hv5v_mcu_sc7 6720 180320 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_23 GF018hv5v_mcu_sc7 6720 188160 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_24 GF018hv5v_mcu_sc7 6720 196000 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_25 GF018hv5v_mcu_sc7 6720 203840 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_26 GF018hv5v_mcu_sc7 6720 211680 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_27 GF018hv5v_mcu_sc7 6720 219520 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_28 GF018hv5v_mcu_sc7 6720 227360 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_29 GF018hv5v_mcu_sc7 6720 235200 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_30 GF018hv5v_mcu_sc7 6720 243040 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_31 GF018hv5v_mcu_sc7 6720 250880 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_32 GF018hv5v_mcu_sc7 6720 258720 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_33 GF018hv5v_mcu_sc7 6720 266560 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_34 GF018hv5v_mcu_sc7 6720 274400 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_35 GF018hv5v_mcu_sc7 6720 282240 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_36 GF018hv5v_mcu_sc7 6720 290080 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_37 GF018hv5v_mcu_sc7 6720 297920 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_38 GF018hv5v_mcu_sc7 6720 305760 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_39 GF018hv5v_mcu_sc7 6720 313600 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_40 GF018hv5v_mcu_sc7 6720 321440 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_41 GF018hv5v_mcu_sc7 6720 329280 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_42 GF018hv5v_mcu_sc7 6720 337120 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_43 GF018hv5v_mcu_sc7 6720 344960 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_44 GF018hv5v_mcu_sc7 6720 352800 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_45 GF018hv5v_mcu_sc7 6720 360640 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_46 GF018hv5v_mcu_sc7 6720 368480 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_47 GF018hv5v_mcu_sc7 6720 376320 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_48 GF018hv5v_mcu_sc7 6720 384160 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_49 GF018hv5v_mcu_sc7 6720 392000 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_50 GF018hv5v_mcu_sc7 6720 399840 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_51 GF018hv5v_mcu_sc7 6720 407680 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_52 GF018hv5v_mcu_sc7 6720 415520 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_53 GF018hv5v_mcu_sc7 6720 423360 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_54 GF018hv5v_mcu_sc7 6720 431200 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_55 GF018hv5v_mcu_sc7 6720 439040 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_56 GF018hv5v_mcu_sc7 6720 446880 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_57 GF018hv5v_mcu_sc7 6720 454720 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_58 GF018hv5v_mcu_sc7 6720 462560 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_59 GF018hv5v_mcu_sc7 6720 470400 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_60 GF018hv5v_mcu_sc7 6720 478240 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_61 GF018hv5v_mcu_sc7 6720 486080 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_62 GF018hv5v_mcu_sc7 6720 493920 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_63 GF018hv5v_mcu_sc7 6720 501760 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_64 GF018hv5v_mcu_sc7 6720 509600 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_65 GF018hv5v_mcu_sc7 6720 517440 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_66 GF018hv5v_mcu_sc7 6720 525280 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_67 GF018hv5v_mcu_sc7 6720 533120 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_68 GF018hv5v_mcu_sc7 6720 540960 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_69 GF018hv5v_mcu_sc7 6720 548800 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_70 GF018hv5v_mcu_sc7 6720 556640 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_71 GF018hv5v_mcu_sc7 6720 564480 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_72 GF018hv5v_mcu_sc7 6720 572320 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_73 GF018hv5v_mcu_sc7 6720 580160 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_74 GF018hv5v_mcu_sc7 6720 588000 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_75 GF018hv5v_mcu_sc7 6720 595840 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_76 GF018hv5v_mcu_sc7 6720 603680 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_77 GF018hv5v_mcu_sc7 6720 611520 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_78 GF018hv5v_mcu_sc7 6720 619360 N DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_79 GF018hv5v_mcu_sc7 6720 627200 FS DO 1258 BY 1 STEP 1120 0 ; +ROW ROW_80 GF018hv5v_mcu_sc7 6720 635040 N DO 1258 BY 1 STEP 1120 0 ; +TRACKS X 560 DO 1270 STEP 1120 LAYER Metal1 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal1 ; +TRACKS X 560 DO 1270 STEP 1120 LAYER Metal2 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal2 ; +TRACKS X 560 DO 1270 STEP 1120 LAYER Metal3 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal3 ; +TRACKS X 560 DO 1270 STEP 1120 LAYER Metal4 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal4 ; +TRACKS X 900 DO 790 STEP 1800 LAYER Metal5 ; +TRACKS Y 900 DO 361 STEP 1800 LAYER Metal5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 51 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 662480 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 677040 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 647920 649720 ) N ; + - ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 654640 1000 ) N ; + - ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 567280 1000 ) N ; + - ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 479920 1000 ) N ; + - ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 392560 1000 ) N ; + - ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 305200 1000 ) N ; + - ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 217840 1000 ) N ; + - ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 130480 1000 ) N ; + - ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 43120 1000 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 633360 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 618800 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 604240 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 589680 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 575120 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 560560 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 546000 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 531440 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 516880 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 502320 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 487760 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 473200 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 458640 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 444080 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 429520 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 414960 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 167440 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 152880 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 138320 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 123760 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 109200 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 94640 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 80080 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 65520 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 283920 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 269360 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 254800 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 240240 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 225680 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 211120 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 196560 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 182000 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 400400 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 385840 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 371280 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 356720 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 342160 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 327600 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 313040 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 298480 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VPWR + USE POWER ; + - VGND + USE GROUND ; +END SPECIALNETS +NETS 51 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ua[0] ( PIN ua[0] ) + USE SIGNAL ; + - ua[1] ( PIN ua[1] ) + USE SIGNAL ; + - ua[2] ( PIN ua[2] ) + USE SIGNAL ; + - ua[3] ( PIN ua[3] ) + USE SIGNAL ; + - ua[4] ( PIN ua[4] ) + USE SIGNAL ; + - ua[5] ( PIN ua[5] ) + USE SIGNAL ; + - ua[6] ( PIN ua[6] ) + USE SIGNAL ; + - ua[7] ( PIN ua[7] ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/analog/tt_analog_2x2_pgvaa.def b/tech/gf180mcuD/def/analog/tt_analog_2x2_pgvaa.def new file mode 100644 index 0000000..818b3fb --- /dev/null +++ b/tech/gf180mcuD/def/analog/tt_analog_2x2_pgvaa.def @@ -0,0 +1,363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 1386560 650720 ) ; +ROW ROW_0 GF018hv5v_mcu_sc7 6720 7840 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_1 GF018hv5v_mcu_sc7 6720 15680 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_2 GF018hv5v_mcu_sc7 6720 23520 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_3 GF018hv5v_mcu_sc7 6720 31360 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_4 GF018hv5v_mcu_sc7 6720 39200 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_5 GF018hv5v_mcu_sc7 6720 47040 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_6 GF018hv5v_mcu_sc7 6720 54880 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_7 GF018hv5v_mcu_sc7 6720 62720 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_8 GF018hv5v_mcu_sc7 6720 70560 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_9 GF018hv5v_mcu_sc7 6720 78400 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_10 GF018hv5v_mcu_sc7 6720 86240 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_11 GF018hv5v_mcu_sc7 6720 94080 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_12 GF018hv5v_mcu_sc7 6720 101920 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_13 GF018hv5v_mcu_sc7 6720 109760 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_14 GF018hv5v_mcu_sc7 6720 117600 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_15 GF018hv5v_mcu_sc7 6720 125440 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_16 GF018hv5v_mcu_sc7 6720 133280 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_17 GF018hv5v_mcu_sc7 6720 141120 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_18 GF018hv5v_mcu_sc7 6720 148960 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_19 GF018hv5v_mcu_sc7 6720 156800 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_20 GF018hv5v_mcu_sc7 6720 164640 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_21 GF018hv5v_mcu_sc7 6720 172480 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_22 GF018hv5v_mcu_sc7 6720 180320 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_23 GF018hv5v_mcu_sc7 6720 188160 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_24 GF018hv5v_mcu_sc7 6720 196000 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_25 GF018hv5v_mcu_sc7 6720 203840 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_26 GF018hv5v_mcu_sc7 6720 211680 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_27 GF018hv5v_mcu_sc7 6720 219520 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_28 GF018hv5v_mcu_sc7 6720 227360 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_29 GF018hv5v_mcu_sc7 6720 235200 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_30 GF018hv5v_mcu_sc7 6720 243040 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_31 GF018hv5v_mcu_sc7 6720 250880 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_32 GF018hv5v_mcu_sc7 6720 258720 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_33 GF018hv5v_mcu_sc7 6720 266560 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_34 GF018hv5v_mcu_sc7 6720 274400 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_35 GF018hv5v_mcu_sc7 6720 282240 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_36 GF018hv5v_mcu_sc7 6720 290080 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_37 GF018hv5v_mcu_sc7 6720 297920 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_38 GF018hv5v_mcu_sc7 6720 305760 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_39 GF018hv5v_mcu_sc7 6720 313600 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_40 GF018hv5v_mcu_sc7 6720 321440 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_41 GF018hv5v_mcu_sc7 6720 329280 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_42 GF018hv5v_mcu_sc7 6720 337120 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_43 GF018hv5v_mcu_sc7 6720 344960 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_44 GF018hv5v_mcu_sc7 6720 352800 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_45 GF018hv5v_mcu_sc7 6720 360640 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_46 GF018hv5v_mcu_sc7 6720 368480 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_47 GF018hv5v_mcu_sc7 6720 376320 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_48 GF018hv5v_mcu_sc7 6720 384160 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_49 GF018hv5v_mcu_sc7 6720 392000 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_50 GF018hv5v_mcu_sc7 6720 399840 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_51 GF018hv5v_mcu_sc7 6720 407680 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_52 GF018hv5v_mcu_sc7 6720 415520 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_53 GF018hv5v_mcu_sc7 6720 423360 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_54 GF018hv5v_mcu_sc7 6720 431200 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_55 GF018hv5v_mcu_sc7 6720 439040 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_56 GF018hv5v_mcu_sc7 6720 446880 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_57 GF018hv5v_mcu_sc7 6720 454720 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_58 GF018hv5v_mcu_sc7 6720 462560 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_59 GF018hv5v_mcu_sc7 6720 470400 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_60 GF018hv5v_mcu_sc7 6720 478240 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_61 GF018hv5v_mcu_sc7 6720 486080 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_62 GF018hv5v_mcu_sc7 6720 493920 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_63 GF018hv5v_mcu_sc7 6720 501760 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_64 GF018hv5v_mcu_sc7 6720 509600 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_65 GF018hv5v_mcu_sc7 6720 517440 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_66 GF018hv5v_mcu_sc7 6720 525280 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_67 GF018hv5v_mcu_sc7 6720 533120 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_68 GF018hv5v_mcu_sc7 6720 540960 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_69 GF018hv5v_mcu_sc7 6720 548800 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_70 GF018hv5v_mcu_sc7 6720 556640 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_71 GF018hv5v_mcu_sc7 6720 564480 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_72 GF018hv5v_mcu_sc7 6720 572320 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_73 GF018hv5v_mcu_sc7 6720 580160 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_74 GF018hv5v_mcu_sc7 6720 588000 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_75 GF018hv5v_mcu_sc7 6720 595840 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_76 GF018hv5v_mcu_sc7 6720 603680 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_77 GF018hv5v_mcu_sc7 6720 611520 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_78 GF018hv5v_mcu_sc7 6720 619360 N DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_79 GF018hv5v_mcu_sc7 6720 627200 FS DO 1226 BY 1 STEP 1120 0 ; +ROW ROW_80 GF018hv5v_mcu_sc7 6720 635040 N DO 1226 BY 1 STEP 1120 0 ; +TRACKS X 560 DO 1238 STEP 1120 LAYER Metal1 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal1 ; +TRACKS X 560 DO 1238 STEP 1120 LAYER Metal2 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal2 ; +TRACKS X 560 DO 1238 STEP 1120 LAYER Metal3 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal3 ; +TRACKS X 560 DO 1238 STEP 1120 LAYER Metal4 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal4 ; +TRACKS X 900 DO 770 STEP 1800 LAYER Metal5 ; +TRACKS Y 900 DO 361 STEP 1800 LAYER Metal5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 51 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626640 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 641200 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 612080 649720 ) N ; + - ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 618800 1000 ) N ; + - ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 531440 1000 ) N ; + - ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 444080 1000 ) N ; + - ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 356720 1000 ) N ; + - ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 269360 1000 ) N ; + - ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 182000 1000 ) N ; + - ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 94640 1000 ) N ; + - ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 7280 1000 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 597520 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582960 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 568400 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553840 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 539280 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524720 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 510160 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495600 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 481040 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 466480 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451920 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 437360 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422800 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 408240 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393680 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 379120 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131600 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 117040 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 102480 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87920 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 73360 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58800 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 44240 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29680 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 248080 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 233520 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218960 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 204400 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189840 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 175280 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160720 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 146160 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364560 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 350000 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 335440 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320880 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 306320 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291760 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 277200 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262640 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VPWR + USE POWER ; + - VGND + USE GROUND ; +END SPECIALNETS +NETS 51 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ua[0] ( PIN ua[0] ) + USE SIGNAL ; + - ua[1] ( PIN ua[1] ) + USE SIGNAL ; + - ua[2] ( PIN ua[2] ) + USE SIGNAL ; + - ua[3] ( PIN ua[3] ) + USE SIGNAL ; + - ua[4] ( PIN ua[4] ) + USE SIGNAL ; + - ua[5] ( PIN ua[5] ) + USE SIGNAL ; + - ua[6] ( PIN ua[6] ) + USE SIGNAL ; + - ua[7] ( PIN ua[7] ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/analog/tt_analog_3x2.def b/tech/gf180mcuD/def/analog/tt_analog_3x2.def new file mode 100644 index 0000000..c816803 --- /dev/null +++ b/tech/gf180mcuD/def/analog/tt_analog_3x2.def @@ -0,0 +1,363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 2151520 650720 ) ; +ROW ROW_0 GF018hv5v_mcu_sc7 6720 7840 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_1 GF018hv5v_mcu_sc7 6720 15680 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_2 GF018hv5v_mcu_sc7 6720 23520 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_3 GF018hv5v_mcu_sc7 6720 31360 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_4 GF018hv5v_mcu_sc7 6720 39200 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_5 GF018hv5v_mcu_sc7 6720 47040 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_6 GF018hv5v_mcu_sc7 6720 54880 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_7 GF018hv5v_mcu_sc7 6720 62720 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_8 GF018hv5v_mcu_sc7 6720 70560 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_9 GF018hv5v_mcu_sc7 6720 78400 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_10 GF018hv5v_mcu_sc7 6720 86240 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_11 GF018hv5v_mcu_sc7 6720 94080 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_12 GF018hv5v_mcu_sc7 6720 101920 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_13 GF018hv5v_mcu_sc7 6720 109760 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_14 GF018hv5v_mcu_sc7 6720 117600 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_15 GF018hv5v_mcu_sc7 6720 125440 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_16 GF018hv5v_mcu_sc7 6720 133280 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_17 GF018hv5v_mcu_sc7 6720 141120 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_18 GF018hv5v_mcu_sc7 6720 148960 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_19 GF018hv5v_mcu_sc7 6720 156800 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_20 GF018hv5v_mcu_sc7 6720 164640 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_21 GF018hv5v_mcu_sc7 6720 172480 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_22 GF018hv5v_mcu_sc7 6720 180320 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_23 GF018hv5v_mcu_sc7 6720 188160 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_24 GF018hv5v_mcu_sc7 6720 196000 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_25 GF018hv5v_mcu_sc7 6720 203840 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_26 GF018hv5v_mcu_sc7 6720 211680 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_27 GF018hv5v_mcu_sc7 6720 219520 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_28 GF018hv5v_mcu_sc7 6720 227360 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_29 GF018hv5v_mcu_sc7 6720 235200 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_30 GF018hv5v_mcu_sc7 6720 243040 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_31 GF018hv5v_mcu_sc7 6720 250880 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_32 GF018hv5v_mcu_sc7 6720 258720 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_33 GF018hv5v_mcu_sc7 6720 266560 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_34 GF018hv5v_mcu_sc7 6720 274400 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_35 GF018hv5v_mcu_sc7 6720 282240 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_36 GF018hv5v_mcu_sc7 6720 290080 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_37 GF018hv5v_mcu_sc7 6720 297920 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_38 GF018hv5v_mcu_sc7 6720 305760 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_39 GF018hv5v_mcu_sc7 6720 313600 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_40 GF018hv5v_mcu_sc7 6720 321440 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_41 GF018hv5v_mcu_sc7 6720 329280 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_42 GF018hv5v_mcu_sc7 6720 337120 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_43 GF018hv5v_mcu_sc7 6720 344960 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_44 GF018hv5v_mcu_sc7 6720 352800 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_45 GF018hv5v_mcu_sc7 6720 360640 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_46 GF018hv5v_mcu_sc7 6720 368480 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_47 GF018hv5v_mcu_sc7 6720 376320 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_48 GF018hv5v_mcu_sc7 6720 384160 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_49 GF018hv5v_mcu_sc7 6720 392000 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_50 GF018hv5v_mcu_sc7 6720 399840 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_51 GF018hv5v_mcu_sc7 6720 407680 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_52 GF018hv5v_mcu_sc7 6720 415520 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_53 GF018hv5v_mcu_sc7 6720 423360 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_54 GF018hv5v_mcu_sc7 6720 431200 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_55 GF018hv5v_mcu_sc7 6720 439040 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_56 GF018hv5v_mcu_sc7 6720 446880 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_57 GF018hv5v_mcu_sc7 6720 454720 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_58 GF018hv5v_mcu_sc7 6720 462560 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_59 GF018hv5v_mcu_sc7 6720 470400 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_60 GF018hv5v_mcu_sc7 6720 478240 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_61 GF018hv5v_mcu_sc7 6720 486080 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_62 GF018hv5v_mcu_sc7 6720 493920 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_63 GF018hv5v_mcu_sc7 6720 501760 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_64 GF018hv5v_mcu_sc7 6720 509600 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_65 GF018hv5v_mcu_sc7 6720 517440 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_66 GF018hv5v_mcu_sc7 6720 525280 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_67 GF018hv5v_mcu_sc7 6720 533120 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_68 GF018hv5v_mcu_sc7 6720 540960 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_69 GF018hv5v_mcu_sc7 6720 548800 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_70 GF018hv5v_mcu_sc7 6720 556640 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_71 GF018hv5v_mcu_sc7 6720 564480 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_72 GF018hv5v_mcu_sc7 6720 572320 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_73 GF018hv5v_mcu_sc7 6720 580160 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_74 GF018hv5v_mcu_sc7 6720 588000 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_75 GF018hv5v_mcu_sc7 6720 595840 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_76 GF018hv5v_mcu_sc7 6720 603680 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_77 GF018hv5v_mcu_sc7 6720 611520 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_78 GF018hv5v_mcu_sc7 6720 619360 N DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_79 GF018hv5v_mcu_sc7 6720 627200 FS DO 1909 BY 1 STEP 1120 0 ; +ROW ROW_80 GF018hv5v_mcu_sc7 6720 635040 N DO 1909 BY 1 STEP 1120 0 ; +TRACKS X 560 DO 1921 STEP 1120 LAYER Metal1 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal1 ; +TRACKS X 560 DO 1921 STEP 1120 LAYER Metal2 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal2 ; +TRACKS X 560 DO 1921 STEP 1120 LAYER Metal3 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal3 ; +TRACKS X 560 DO 1921 STEP 1120 LAYER Metal4 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal4 ; +TRACKS X 900 DO 1195 STEP 1800 LAYER Metal5 ; +TRACKS Y 900 DO 361 STEP 1800 LAYER Metal5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 51 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 662480 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 677040 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 647920 649720 ) N ; + - ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 654640 1000 ) N ; + - ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 567280 1000 ) N ; + - ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 479920 1000 ) N ; + - ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 392560 1000 ) N ; + - ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 305200 1000 ) N ; + - ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 217840 1000 ) N ; + - ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 130480 1000 ) N ; + - ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 43120 1000 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 633360 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 618800 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 604240 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 589680 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 575120 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 560560 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 546000 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 531440 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 516880 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 502320 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 487760 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 473200 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 458640 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 444080 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 429520 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 414960 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 167440 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 152880 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 138320 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 123760 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 109200 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 94640 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 80080 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 65520 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 283920 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 269360 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 254800 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 240240 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 225680 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 211120 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 196560 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 182000 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 400400 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 385840 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 371280 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 356720 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 342160 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 327600 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 313040 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 298480 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VPWR + USE POWER ; + - VGND + USE GROUND ; +END SPECIALNETS +NETS 51 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ua[0] ( PIN ua[0] ) + USE SIGNAL ; + - ua[1] ( PIN ua[1] ) + USE SIGNAL ; + - ua[2] ( PIN ua[2] ) + USE SIGNAL ; + - ua[3] ( PIN ua[3] ) + USE SIGNAL ; + - ua[4] ( PIN ua[4] ) + USE SIGNAL ; + - ua[5] ( PIN ua[5] ) + USE SIGNAL ; + - ua[6] ( PIN ua[6] ) + USE SIGNAL ; + - ua[7] ( PIN ua[7] ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/analog/tt_analog_3x2_pgvaa.def b/tech/gf180mcuD/def/analog/tt_analog_3x2_pgvaa.def new file mode 100644 index 0000000..556d1a9 --- /dev/null +++ b/tech/gf180mcuD/def/analog/tt_analog_3x2_pgvaa.def @@ -0,0 +1,363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 2115680 650720 ) ; +ROW ROW_0 GF018hv5v_mcu_sc7 6720 7840 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_1 GF018hv5v_mcu_sc7 6720 15680 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_2 GF018hv5v_mcu_sc7 6720 23520 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_3 GF018hv5v_mcu_sc7 6720 31360 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_4 GF018hv5v_mcu_sc7 6720 39200 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_5 GF018hv5v_mcu_sc7 6720 47040 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_6 GF018hv5v_mcu_sc7 6720 54880 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_7 GF018hv5v_mcu_sc7 6720 62720 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_8 GF018hv5v_mcu_sc7 6720 70560 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_9 GF018hv5v_mcu_sc7 6720 78400 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_10 GF018hv5v_mcu_sc7 6720 86240 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_11 GF018hv5v_mcu_sc7 6720 94080 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_12 GF018hv5v_mcu_sc7 6720 101920 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_13 GF018hv5v_mcu_sc7 6720 109760 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_14 GF018hv5v_mcu_sc7 6720 117600 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_15 GF018hv5v_mcu_sc7 6720 125440 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_16 GF018hv5v_mcu_sc7 6720 133280 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_17 GF018hv5v_mcu_sc7 6720 141120 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_18 GF018hv5v_mcu_sc7 6720 148960 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_19 GF018hv5v_mcu_sc7 6720 156800 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_20 GF018hv5v_mcu_sc7 6720 164640 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_21 GF018hv5v_mcu_sc7 6720 172480 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_22 GF018hv5v_mcu_sc7 6720 180320 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_23 GF018hv5v_mcu_sc7 6720 188160 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_24 GF018hv5v_mcu_sc7 6720 196000 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_25 GF018hv5v_mcu_sc7 6720 203840 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_26 GF018hv5v_mcu_sc7 6720 211680 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_27 GF018hv5v_mcu_sc7 6720 219520 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_28 GF018hv5v_mcu_sc7 6720 227360 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_29 GF018hv5v_mcu_sc7 6720 235200 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_30 GF018hv5v_mcu_sc7 6720 243040 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_31 GF018hv5v_mcu_sc7 6720 250880 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_32 GF018hv5v_mcu_sc7 6720 258720 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_33 GF018hv5v_mcu_sc7 6720 266560 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_34 GF018hv5v_mcu_sc7 6720 274400 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_35 GF018hv5v_mcu_sc7 6720 282240 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_36 GF018hv5v_mcu_sc7 6720 290080 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_37 GF018hv5v_mcu_sc7 6720 297920 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_38 GF018hv5v_mcu_sc7 6720 305760 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_39 GF018hv5v_mcu_sc7 6720 313600 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_40 GF018hv5v_mcu_sc7 6720 321440 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_41 GF018hv5v_mcu_sc7 6720 329280 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_42 GF018hv5v_mcu_sc7 6720 337120 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_43 GF018hv5v_mcu_sc7 6720 344960 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_44 GF018hv5v_mcu_sc7 6720 352800 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_45 GF018hv5v_mcu_sc7 6720 360640 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_46 GF018hv5v_mcu_sc7 6720 368480 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_47 GF018hv5v_mcu_sc7 6720 376320 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_48 GF018hv5v_mcu_sc7 6720 384160 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_49 GF018hv5v_mcu_sc7 6720 392000 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_50 GF018hv5v_mcu_sc7 6720 399840 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_51 GF018hv5v_mcu_sc7 6720 407680 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_52 GF018hv5v_mcu_sc7 6720 415520 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_53 GF018hv5v_mcu_sc7 6720 423360 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_54 GF018hv5v_mcu_sc7 6720 431200 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_55 GF018hv5v_mcu_sc7 6720 439040 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_56 GF018hv5v_mcu_sc7 6720 446880 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_57 GF018hv5v_mcu_sc7 6720 454720 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_58 GF018hv5v_mcu_sc7 6720 462560 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_59 GF018hv5v_mcu_sc7 6720 470400 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_60 GF018hv5v_mcu_sc7 6720 478240 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_61 GF018hv5v_mcu_sc7 6720 486080 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_62 GF018hv5v_mcu_sc7 6720 493920 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_63 GF018hv5v_mcu_sc7 6720 501760 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_64 GF018hv5v_mcu_sc7 6720 509600 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_65 GF018hv5v_mcu_sc7 6720 517440 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_66 GF018hv5v_mcu_sc7 6720 525280 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_67 GF018hv5v_mcu_sc7 6720 533120 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_68 GF018hv5v_mcu_sc7 6720 540960 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_69 GF018hv5v_mcu_sc7 6720 548800 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_70 GF018hv5v_mcu_sc7 6720 556640 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_71 GF018hv5v_mcu_sc7 6720 564480 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_72 GF018hv5v_mcu_sc7 6720 572320 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_73 GF018hv5v_mcu_sc7 6720 580160 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_74 GF018hv5v_mcu_sc7 6720 588000 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_75 GF018hv5v_mcu_sc7 6720 595840 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_76 GF018hv5v_mcu_sc7 6720 603680 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_77 GF018hv5v_mcu_sc7 6720 611520 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_78 GF018hv5v_mcu_sc7 6720 619360 N DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_79 GF018hv5v_mcu_sc7 6720 627200 FS DO 1877 BY 1 STEP 1120 0 ; +ROW ROW_80 GF018hv5v_mcu_sc7 6720 635040 N DO 1877 BY 1 STEP 1120 0 ; +TRACKS X 560 DO 1889 STEP 1120 LAYER Metal1 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal1 ; +TRACKS X 560 DO 1889 STEP 1120 LAYER Metal2 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal2 ; +TRACKS X 560 DO 1889 STEP 1120 LAYER Metal3 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal3 ; +TRACKS X 560 DO 1889 STEP 1120 LAYER Metal4 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal4 ; +TRACKS X 900 DO 1175 STEP 1800 LAYER Metal5 ; +TRACKS Y 900 DO 361 STEP 1800 LAYER Metal5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 51 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626640 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 641200 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 612080 649720 ) N ; + - ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 618800 1000 ) N ; + - ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 531440 1000 ) N ; + - ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 444080 1000 ) N ; + - ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 356720 1000 ) N ; + - ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 269360 1000 ) N ; + - ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 182000 1000 ) N ; + - ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 94640 1000 ) N ; + - ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 7280 1000 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 597520 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582960 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 568400 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553840 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 539280 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524720 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 510160 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495600 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 481040 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 466480 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451920 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 437360 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422800 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 408240 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393680 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 379120 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131600 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 117040 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 102480 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87920 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 73360 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58800 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 44240 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29680 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 248080 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 233520 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218960 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 204400 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189840 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 175280 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160720 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 146160 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364560 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 350000 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 335440 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320880 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 306320 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291760 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 277200 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262640 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VPWR + USE POWER ; + - VGND + USE GROUND ; +END SPECIALNETS +NETS 51 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ua[0] ( PIN ua[0] ) + USE SIGNAL ; + - ua[1] ( PIN ua[1] ) + USE SIGNAL ; + - ua[2] ( PIN ua[2] ) + USE SIGNAL ; + - ua[3] ( PIN ua[3] ) + USE SIGNAL ; + - ua[4] ( PIN ua[4] ) + USE SIGNAL ; + - ua[5] ( PIN ua[5] ) + USE SIGNAL ; + - ua[6] ( PIN ua[6] ) + USE SIGNAL ; + - ua[7] ( PIN ua[7] ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/analog/tt_analog_4x2.def b/tech/gf180mcuD/def/analog/tt_analog_4x2.def new file mode 100644 index 0000000..63b47c3 --- /dev/null +++ b/tech/gf180mcuD/def/analog/tt_analog_4x2.def @@ -0,0 +1,363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 2880640 650720 ) ; +ROW ROW_0 GF018hv5v_mcu_sc7 6720 7840 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_1 GF018hv5v_mcu_sc7 6720 15680 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_2 GF018hv5v_mcu_sc7 6720 23520 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_3 GF018hv5v_mcu_sc7 6720 31360 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_4 GF018hv5v_mcu_sc7 6720 39200 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_5 GF018hv5v_mcu_sc7 6720 47040 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_6 GF018hv5v_mcu_sc7 6720 54880 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_7 GF018hv5v_mcu_sc7 6720 62720 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_8 GF018hv5v_mcu_sc7 6720 70560 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_9 GF018hv5v_mcu_sc7 6720 78400 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_10 GF018hv5v_mcu_sc7 6720 86240 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_11 GF018hv5v_mcu_sc7 6720 94080 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_12 GF018hv5v_mcu_sc7 6720 101920 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_13 GF018hv5v_mcu_sc7 6720 109760 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_14 GF018hv5v_mcu_sc7 6720 117600 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_15 GF018hv5v_mcu_sc7 6720 125440 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_16 GF018hv5v_mcu_sc7 6720 133280 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_17 GF018hv5v_mcu_sc7 6720 141120 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_18 GF018hv5v_mcu_sc7 6720 148960 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_19 GF018hv5v_mcu_sc7 6720 156800 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_20 GF018hv5v_mcu_sc7 6720 164640 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_21 GF018hv5v_mcu_sc7 6720 172480 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_22 GF018hv5v_mcu_sc7 6720 180320 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_23 GF018hv5v_mcu_sc7 6720 188160 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_24 GF018hv5v_mcu_sc7 6720 196000 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_25 GF018hv5v_mcu_sc7 6720 203840 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_26 GF018hv5v_mcu_sc7 6720 211680 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_27 GF018hv5v_mcu_sc7 6720 219520 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_28 GF018hv5v_mcu_sc7 6720 227360 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_29 GF018hv5v_mcu_sc7 6720 235200 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_30 GF018hv5v_mcu_sc7 6720 243040 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_31 GF018hv5v_mcu_sc7 6720 250880 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_32 GF018hv5v_mcu_sc7 6720 258720 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_33 GF018hv5v_mcu_sc7 6720 266560 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_34 GF018hv5v_mcu_sc7 6720 274400 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_35 GF018hv5v_mcu_sc7 6720 282240 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_36 GF018hv5v_mcu_sc7 6720 290080 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_37 GF018hv5v_mcu_sc7 6720 297920 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_38 GF018hv5v_mcu_sc7 6720 305760 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_39 GF018hv5v_mcu_sc7 6720 313600 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_40 GF018hv5v_mcu_sc7 6720 321440 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_41 GF018hv5v_mcu_sc7 6720 329280 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_42 GF018hv5v_mcu_sc7 6720 337120 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_43 GF018hv5v_mcu_sc7 6720 344960 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_44 GF018hv5v_mcu_sc7 6720 352800 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_45 GF018hv5v_mcu_sc7 6720 360640 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_46 GF018hv5v_mcu_sc7 6720 368480 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_47 GF018hv5v_mcu_sc7 6720 376320 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_48 GF018hv5v_mcu_sc7 6720 384160 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_49 GF018hv5v_mcu_sc7 6720 392000 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_50 GF018hv5v_mcu_sc7 6720 399840 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_51 GF018hv5v_mcu_sc7 6720 407680 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_52 GF018hv5v_mcu_sc7 6720 415520 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_53 GF018hv5v_mcu_sc7 6720 423360 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_54 GF018hv5v_mcu_sc7 6720 431200 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_55 GF018hv5v_mcu_sc7 6720 439040 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_56 GF018hv5v_mcu_sc7 6720 446880 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_57 GF018hv5v_mcu_sc7 6720 454720 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_58 GF018hv5v_mcu_sc7 6720 462560 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_59 GF018hv5v_mcu_sc7 6720 470400 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_60 GF018hv5v_mcu_sc7 6720 478240 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_61 GF018hv5v_mcu_sc7 6720 486080 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_62 GF018hv5v_mcu_sc7 6720 493920 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_63 GF018hv5v_mcu_sc7 6720 501760 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_64 GF018hv5v_mcu_sc7 6720 509600 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_65 GF018hv5v_mcu_sc7 6720 517440 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_66 GF018hv5v_mcu_sc7 6720 525280 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_67 GF018hv5v_mcu_sc7 6720 533120 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_68 GF018hv5v_mcu_sc7 6720 540960 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_69 GF018hv5v_mcu_sc7 6720 548800 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_70 GF018hv5v_mcu_sc7 6720 556640 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_71 GF018hv5v_mcu_sc7 6720 564480 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_72 GF018hv5v_mcu_sc7 6720 572320 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_73 GF018hv5v_mcu_sc7 6720 580160 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_74 GF018hv5v_mcu_sc7 6720 588000 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_75 GF018hv5v_mcu_sc7 6720 595840 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_76 GF018hv5v_mcu_sc7 6720 603680 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_77 GF018hv5v_mcu_sc7 6720 611520 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_78 GF018hv5v_mcu_sc7 6720 619360 N DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_79 GF018hv5v_mcu_sc7 6720 627200 FS DO 2560 BY 1 STEP 1120 0 ; +ROW ROW_80 GF018hv5v_mcu_sc7 6720 635040 N DO 2560 BY 1 STEP 1120 0 ; +TRACKS X 560 DO 2572 STEP 1120 LAYER Metal1 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal1 ; +TRACKS X 560 DO 2572 STEP 1120 LAYER Metal2 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal2 ; +TRACKS X 560 DO 2572 STEP 1120 LAYER Metal3 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal3 ; +TRACKS X 560 DO 2572 STEP 1120 LAYER Metal4 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal4 ; +TRACKS X 900 DO 1600 STEP 1800 LAYER Metal5 ; +TRACKS Y 900 DO 361 STEP 1800 LAYER Metal5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 51 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 662480 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 677040 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 647920 649720 ) N ; + - ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 654640 1000 ) N ; + - ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 567280 1000 ) N ; + - ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 479920 1000 ) N ; + - ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 392560 1000 ) N ; + - ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 305200 1000 ) N ; + - ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 217840 1000 ) N ; + - ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 130480 1000 ) N ; + - ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 43120 1000 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 633360 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 618800 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 604240 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 589680 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 575120 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 560560 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 546000 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 531440 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 516880 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 502320 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 487760 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 473200 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 458640 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 444080 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 429520 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 414960 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 167440 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 152880 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 138320 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 123760 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 109200 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 94640 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 80080 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 65520 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 283920 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 269360 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 254800 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 240240 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 225680 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 211120 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 196560 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 182000 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 400400 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 385840 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 371280 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 356720 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 342160 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 327600 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 313040 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 298480 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VPWR + USE POWER ; + - VGND + USE GROUND ; +END SPECIALNETS +NETS 51 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ua[0] ( PIN ua[0] ) + USE SIGNAL ; + - ua[1] ( PIN ua[1] ) + USE SIGNAL ; + - ua[2] ( PIN ua[2] ) + USE SIGNAL ; + - ua[3] ( PIN ua[3] ) + USE SIGNAL ; + - ua[4] ( PIN ua[4] ) + USE SIGNAL ; + - ua[5] ( PIN ua[5] ) + USE SIGNAL ; + - ua[6] ( PIN ua[6] ) + USE SIGNAL ; + - ua[7] ( PIN ua[7] ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/analog/tt_analog_4x2_pgvaa.def b/tech/gf180mcuD/def/analog/tt_analog_4x2_pgvaa.def new file mode 100644 index 0000000..bd9f5fc --- /dev/null +++ b/tech/gf180mcuD/def/analog/tt_analog_4x2_pgvaa.def @@ -0,0 +1,363 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 2844800 650720 ) ; +ROW ROW_0 GF018hv5v_mcu_sc7 6720 7840 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_1 GF018hv5v_mcu_sc7 6720 15680 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_2 GF018hv5v_mcu_sc7 6720 23520 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_3 GF018hv5v_mcu_sc7 6720 31360 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_4 GF018hv5v_mcu_sc7 6720 39200 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_5 GF018hv5v_mcu_sc7 6720 47040 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_6 GF018hv5v_mcu_sc7 6720 54880 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_7 GF018hv5v_mcu_sc7 6720 62720 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_8 GF018hv5v_mcu_sc7 6720 70560 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_9 GF018hv5v_mcu_sc7 6720 78400 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_10 GF018hv5v_mcu_sc7 6720 86240 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_11 GF018hv5v_mcu_sc7 6720 94080 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_12 GF018hv5v_mcu_sc7 6720 101920 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_13 GF018hv5v_mcu_sc7 6720 109760 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_14 GF018hv5v_mcu_sc7 6720 117600 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_15 GF018hv5v_mcu_sc7 6720 125440 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_16 GF018hv5v_mcu_sc7 6720 133280 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_17 GF018hv5v_mcu_sc7 6720 141120 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_18 GF018hv5v_mcu_sc7 6720 148960 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_19 GF018hv5v_mcu_sc7 6720 156800 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_20 GF018hv5v_mcu_sc7 6720 164640 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_21 GF018hv5v_mcu_sc7 6720 172480 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_22 GF018hv5v_mcu_sc7 6720 180320 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_23 GF018hv5v_mcu_sc7 6720 188160 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_24 GF018hv5v_mcu_sc7 6720 196000 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_25 GF018hv5v_mcu_sc7 6720 203840 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_26 GF018hv5v_mcu_sc7 6720 211680 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_27 GF018hv5v_mcu_sc7 6720 219520 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_28 GF018hv5v_mcu_sc7 6720 227360 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_29 GF018hv5v_mcu_sc7 6720 235200 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_30 GF018hv5v_mcu_sc7 6720 243040 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_31 GF018hv5v_mcu_sc7 6720 250880 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_32 GF018hv5v_mcu_sc7 6720 258720 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_33 GF018hv5v_mcu_sc7 6720 266560 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_34 GF018hv5v_mcu_sc7 6720 274400 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_35 GF018hv5v_mcu_sc7 6720 282240 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_36 GF018hv5v_mcu_sc7 6720 290080 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_37 GF018hv5v_mcu_sc7 6720 297920 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_38 GF018hv5v_mcu_sc7 6720 305760 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_39 GF018hv5v_mcu_sc7 6720 313600 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_40 GF018hv5v_mcu_sc7 6720 321440 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_41 GF018hv5v_mcu_sc7 6720 329280 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_42 GF018hv5v_mcu_sc7 6720 337120 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_43 GF018hv5v_mcu_sc7 6720 344960 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_44 GF018hv5v_mcu_sc7 6720 352800 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_45 GF018hv5v_mcu_sc7 6720 360640 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_46 GF018hv5v_mcu_sc7 6720 368480 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_47 GF018hv5v_mcu_sc7 6720 376320 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_48 GF018hv5v_mcu_sc7 6720 384160 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_49 GF018hv5v_mcu_sc7 6720 392000 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_50 GF018hv5v_mcu_sc7 6720 399840 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_51 GF018hv5v_mcu_sc7 6720 407680 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_52 GF018hv5v_mcu_sc7 6720 415520 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_53 GF018hv5v_mcu_sc7 6720 423360 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_54 GF018hv5v_mcu_sc7 6720 431200 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_55 GF018hv5v_mcu_sc7 6720 439040 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_56 GF018hv5v_mcu_sc7 6720 446880 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_57 GF018hv5v_mcu_sc7 6720 454720 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_58 GF018hv5v_mcu_sc7 6720 462560 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_59 GF018hv5v_mcu_sc7 6720 470400 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_60 GF018hv5v_mcu_sc7 6720 478240 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_61 GF018hv5v_mcu_sc7 6720 486080 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_62 GF018hv5v_mcu_sc7 6720 493920 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_63 GF018hv5v_mcu_sc7 6720 501760 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_64 GF018hv5v_mcu_sc7 6720 509600 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_65 GF018hv5v_mcu_sc7 6720 517440 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_66 GF018hv5v_mcu_sc7 6720 525280 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_67 GF018hv5v_mcu_sc7 6720 533120 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_68 GF018hv5v_mcu_sc7 6720 540960 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_69 GF018hv5v_mcu_sc7 6720 548800 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_70 GF018hv5v_mcu_sc7 6720 556640 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_71 GF018hv5v_mcu_sc7 6720 564480 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_72 GF018hv5v_mcu_sc7 6720 572320 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_73 GF018hv5v_mcu_sc7 6720 580160 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_74 GF018hv5v_mcu_sc7 6720 588000 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_75 GF018hv5v_mcu_sc7 6720 595840 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_76 GF018hv5v_mcu_sc7 6720 603680 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_77 GF018hv5v_mcu_sc7 6720 611520 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_78 GF018hv5v_mcu_sc7 6720 619360 N DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_79 GF018hv5v_mcu_sc7 6720 627200 FS DO 2528 BY 1 STEP 1120 0 ; +ROW ROW_80 GF018hv5v_mcu_sc7 6720 635040 N DO 2528 BY 1 STEP 1120 0 ; +TRACKS X 560 DO 2540 STEP 1120 LAYER Metal1 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal1 ; +TRACKS X 560 DO 2540 STEP 1120 LAYER Metal2 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal2 ; +TRACKS X 560 DO 2540 STEP 1120 LAYER Metal3 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal3 ; +TRACKS X 560 DO 2540 STEP 1120 LAYER Metal4 ; +TRACKS Y 560 DO 581 STEP 1120 LAYER Metal4 ; +TRACKS X 900 DO 1580 STEP 1800 LAYER Metal5 ; +TRACKS Y 900 DO 361 STEP 1800 LAYER Metal5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 51 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626640 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 641200 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 612080 649720 ) N ; + - ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 618800 1000 ) N ; + - ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 531440 1000 ) N ; + - ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 444080 1000 ) N ; + - ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 356720 1000 ) N ; + - ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 269360 1000 ) N ; + - ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 182000 1000 ) N ; + - ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 94640 1000 ) N ; + - ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -3000 -1000 ) ( 3000 1000 ) + + PLACED ( 7280 1000 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 597520 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582960 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 568400 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553840 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 539280 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524720 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 510160 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495600 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 481040 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 466480 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451920 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 437360 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422800 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 408240 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393680 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 379120 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131600 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 117040 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 102480 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87920 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 73360 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58800 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 44240 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29680 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 248080 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 233520 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218960 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 204400 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189840 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 175280 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160720 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 146160 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364560 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 350000 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 335440 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320880 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 306320 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291760 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 277200 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262640 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VPWR + USE POWER ; + - VGND + USE GROUND ; +END SPECIALNETS +NETS 51 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ua[0] ( PIN ua[0] ) + USE SIGNAL ; + - ua[1] ( PIN ua[1] ) + USE SIGNAL ; + - ua[2] ( PIN ua[2] ) + USE SIGNAL ; + - ua[3] ( PIN ua[3] ) + USE SIGNAL ; + - ua[4] ( PIN ua[4] ) + USE SIGNAL ; + - ua[5] ( PIN ua[5] ) + USE SIGNAL ; + - ua[6] ( PIN ua[6] ) + USE SIGNAL ; + - ua[7] ( PIN ua[7] ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN From d5b156e241b2e2f4e257bc322e53929453da1230 Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Sun, 31 May 2026 15:38:22 +0300 Subject: [PATCH 2/3] feat(precheck/gf180mcuD): analog template selection + pin check --- precheck/precheck.py | 11 ++++++++--- precheck/tech_data.py | 11 +++++++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/precheck/precheck.py b/precheck/precheck.py index ef6cb87..68bc1fa 100644 --- a/precheck/precheck.py +++ b/precheck/precheck.py @@ -399,10 +399,15 @@ def main(): raise PrecheckFailure("Projects with 3v3 power need at least one analog pin") def_root = f"../tech/{tech}/def" if is_analog: + analog_def = f"{def_root}/analog/tt_analog_{tiles}" if uses_3v3: - template_def = f"{def_root}/analog/tt_analog_{tiles}_3v3.def" + # gf180's second supply rail is "pgvaa" (its core is already 3v3, so + # "_3v3" is a misnomer); fall back to "_3v3" for techs that use it. + template_def = f"{analog_def}_pgvaa.def" + if not os.path.exists(template_def): + template_def = f"{analog_def}_3v3.def" else: - template_def = f"{def_root}/analog/tt_analog_{tiles}.def" + template_def = f"{analog_def}.def" elif tech == "ihp-sg13g2" or tech == "gf180mcuD": template_def = f"{def_root}/tt_block_{tiles}_pgvdd.def" else: @@ -486,7 +491,7 @@ def main(): "check": lambda: analog_pin_check( gds_file, tech, is_analog, uses_3v3, analog_pins, pinout ), - "techs": ["sky130A", "ihp-sg13g2"], + "techs": ["sky130A", "ihp-sg13g2", "gf180mcuD"], }, { "name": "Verilog syntax check", diff --git a/precheck/tech_data.py b/precheck/tech_data.py index e0facb8..a1a177c 100644 --- a/precheck/tech_data.py +++ b/precheck/tech_data.py @@ -119,6 +119,17 @@ def analog_pin_rects(tech: str, uses_3v3: bool): x2, y2 = x1 + 1.75, y1 + 2.0 rect = ((x1, y1), (x2, y2)) yield (rect, pin_layer, via_layers) + elif tech == "gf180mcuD": + pin_layer = (46, 0) # Metal4 + via_layers = [(40, 0)] # Via3 + for pin_number in range(8): + if uses_3v3: + x1, y1 = 307.90 - 43.68 * pin_number, 0.0 + else: + x1, y1 = 325.82 - 43.68 * pin_number, 0.0 + x2, y2 = x1 + 3.0, y1 + 1.0 + rect = ((x1, y1), (x2, y2)) + yield (rect, pin_layer, via_layers) elif tech in tech_names: raise NotImplementedError else: From ed2685479378d441480c0f896d2a9fc7a0d5d16b Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Sun, 31 May 2026 16:18:24 +0300 Subject: [PATCH 3/3] refactor: rename uses_3v3 to uses_vapwr The flag enables a second power supply (VAPWR), not necessarily 3.3V (gf180's core is already 3v3), so "uses_3v3" no longer accurately describes its purpose. Rename it across project_info, precheck, project and shuttle, and update the validation message accordingly. The legacy "uses_3v3" key is still accepted when reading info.yaml, so existing project configs keep working. --- precheck/pin_check.py | 6 +++--- precheck/precheck.py | 35 +++++++++++++++++++++-------------- precheck/tech_data.py | 8 ++++---- precheck/test_precheck.py | 8 ++++---- project.py | 4 ++-- project_info.py | 11 +++++++---- shuttle.py | 2 +- test_project_info.py | 33 ++++++++++++++++++++++----------- 8 files changed, 64 insertions(+), 43 deletions(-) diff --git a/precheck/pin_check.py b/precheck/pin_check.py index aa85fa5..b7fac07 100644 --- a/precheck/pin_check.py +++ b/precheck/pin_check.py @@ -112,14 +112,14 @@ def parse_dbu_to_nm(value: str, dbu_per_micron: int): def pin_check( - gds: str, lef: str, template_def: str, toplevel: str, uses_3v3: bool, tech: str + gds: str, lef: str, template_def: str, toplevel: str, uses_vapwr: bool, tech: str ): logging.info("Running pin check...") logging.info(f"* gds: {gds}") logging.info(f"* lef: {lef}") logging.info(f"* template_def: {template_def}") logging.info(f"* toplevel: {toplevel}") - logging.info(f"* uses_3v3: {uses_3v3}") + logging.info(f"* uses_vapwr: {uses_vapwr}") # parse pins from template def # def syntax: https://coriolis.lip6.fr/doc/lefdef/lefdefref/DEFSyntax.html @@ -201,7 +201,7 @@ def pin_check( rect_re = re.compile(r"RECT (\S+) (\S+) (\S+) (\S+) ;") power_pins = ["VGND", "VDPWR"] - if uses_3v3: + if uses_vapwr: power_pins.append("VAPWR") compat_pins = {"VPWR": "VDPWR"} diff --git a/precheck/precheck.py b/precheck/precheck.py index 68bc1fa..5ab5444 100644 --- a/precheck/precheck.py +++ b/precheck/precheck.py @@ -181,9 +181,9 @@ def boundary_check(gds: str, tech: str): raise PrecheckFailure("Shapes outside project area") -def power_pin_check(verilog: str, lef: str, uses_3v3: bool): +def power_pin_check(verilog: str, lef: str, uses_vapwr: bool): """Ensure that VPWR / VGND are present and have USE definitions, - and that VAPWR is present if and only if 'uses_3v3' is set.""" + and that VAPWR is present if and only if 'uses_vapwr' is set.""" verilog_s = open(verilog).read().replace("VPWR", "VDPWR") lef_s = open(lef).read().replace("VPWR", "VDPWR") @@ -198,7 +198,7 @@ def power_pin_check(verilog: str, lef: str, uses_3v3: bool): ) for ft, s in (("Verilog", verilog_s), ("LEF", lef_s)): - for pwr, ex in (("VGND", True), ("VDPWR", True), ("VAPWR", uses_3v3)): + for pwr, ex in (("VGND", True), ("VDPWR", True), ("VAPWR", uses_vapwr)): if (pwr in s) and not ex: raise PrecheckFailure(f"{ft} contains {pwr}") if not (pwr in s) and ex: @@ -269,7 +269,12 @@ def urpm_nwell_check(gds: str, top_module: str): def analog_pin_check( - gds: str, tech: str, is_analog: bool, uses_3v3: bool, analog_pins: int, pinout: dict + gds: str, + tech: str, + is_analog: bool, + uses_vapwr: bool, + analog_pins: int, + pinout: dict, ): """Check that every analog pin connects to a piece of metal if and only if the pin is used according to info.yaml.""" @@ -279,7 +284,7 @@ def analog_pin_check( filtered = {} for pin, (rect, pin_layer, via_layers) in enumerate( - analog_pin_rects(tech, uses_3v3) + analog_pin_rects(tech, uses_vapwr) ): for layer in [pin_layer] + via_layers: if layer not in filtered: @@ -390,17 +395,19 @@ def main(): top_module = yaml_data["project"].get("top_module", f"tt_um_wokwi_{wokwi_id}") assert top_module == os.path.basename(gds_stem) - tiles = yaml_data.get("project", {}).get("tiles", "1x1") - analog_pins = yaml_data.get("project", {}).get("analog_pins", 0) + project_cfg = yaml_data.get("project", {}) + tiles = project_cfg.get("tiles", "1x1") + analog_pins = project_cfg.get("analog_pins", 0) is_analog = analog_pins > 0 - uses_3v3 = bool(yaml_data.get("project", {}).get("uses_3v3", False)) + # "uses_3v3" is the legacy name for "uses_vapwr"; still accepted for compat. + uses_vapwr = bool(project_cfg.get("uses_vapwr", project_cfg.get("uses_3v3", False))) pinout = yaml_data.get("pinout", {}) - if uses_3v3 and not is_analog: - raise PrecheckFailure("Projects with 3v3 power need at least one analog pin") + if uses_vapwr and not is_analog: + raise PrecheckFailure("Projects with VAPWR power need at least one analog pin") def_root = f"../tech/{tech}/def" if is_analog: analog_def = f"{def_root}/analog/tt_analog_{tiles}" - if uses_3v3: + if uses_vapwr: # gf180's second supply rail is "pgvaa" (its core is already 3v3, so # "_3v3" is a misnomer); fall back to "_3v3" for techs that use it. template_def = f"{analog_def}_pgvaa.def" @@ -465,13 +472,13 @@ def main(): { "name": "Pin check", "check": lambda: pin_check( - gds_file, lef_file, template_def, top_module, uses_3v3, tech + gds_file, lef_file, template_def, top_module, uses_vapwr, tech ), }, {"name": "Boundary check", "check": lambda: boundary_check(gds_file, tech)}, { "name": "Power pin check", - "check": lambda: power_pin_check(verilog_file, lef_file, uses_3v3), + "check": lambda: power_pin_check(verilog_file, lef_file, uses_vapwr), "techs": ["sky130A", "gf180mcuD"], }, {"name": "Layer check", "check": lambda: layer_check(gds_file, tech)}, @@ -489,7 +496,7 @@ def main(): { "name": "Analog pin check", "check": lambda: analog_pin_check( - gds_file, tech, is_analog, uses_3v3, analog_pins, pinout + gds_file, tech, is_analog, uses_vapwr, analog_pins, pinout ), "techs": ["sky130A", "ihp-sg13g2", "gf180mcuD"], }, diff --git a/precheck/tech_data.py b/precheck/tech_data.py index a1a177c..20540cb 100644 --- a/precheck/tech_data.py +++ b/precheck/tech_data.py @@ -96,12 +96,12 @@ valid_layers_gf180mcuD = [ # fmt: on -def analog_pin_rects(tech: str, uses_3v3: bool): +def analog_pin_rects(tech: str, uses_vapwr: bool): if tech == "sky130A": pin_layer = (71, 20) # met4 via_layers = [(70, 44)] # via3 for pin_number in range(8): - if uses_3v3: + if uses_vapwr: x1, y1 = 136.17 - 19.32 * pin_number, 0.0 else: x1, y1 = 151.81 - 19.32 * pin_number, 0.0 @@ -112,7 +112,7 @@ def analog_pin_rects(tech: str, uses_3v3: bool): pin_layer = (126, 0) # TopMetal1 via_layers = [(125, 0)] # TopVia1 for pin_number in range(8): - if uses_3v3: + if uses_vapwr: raise NotImplementedError else: x1, y1 = 190.165 - 24.48 * pin_number, 0.0 @@ -123,7 +123,7 @@ def analog_pin_rects(tech: str, uses_3v3: bool): pin_layer = (46, 0) # Metal4 via_layers = [(40, 0)] # Via3 for pin_number in range(8): - if uses_3v3: + if uses_vapwr: x1, y1 = 307.90 - 43.68 * pin_number, 0.0 else: x1, y1 = 325.82 - 43.68 * pin_number, 0.0 diff --git a/precheck/test_precheck.py b/precheck/test_precheck.py index be394e5..8a5ae0e 100644 --- a/precheck/test_precheck.py +++ b/precheck/test_precheck.py @@ -697,13 +697,13 @@ def test_shapes_outside_area(gds_shapes_outside_area: str): def test_wrong_power_pins_1(verilog_lef_wrong_power_pins: tuple[str, str]): verilog_file, lef_file = verilog_lef_wrong_power_pins with pytest.raises(precheck.PrecheckFailure, match="Verilog contains VAPWR"): - precheck.power_pin_check(verilog_file, lef_file, uses_3v3=False) + precheck.power_pin_check(verilog_file, lef_file, uses_vapwr=False) def test_wrong_power_pins_2(verilog_lef_wrong_power_pins: tuple[str, str]): verilog_file, lef_file = verilog_lef_wrong_power_pins with pytest.raises(precheck.PrecheckFailure, match="LEF doesn't contain VAPWR"): - precheck.power_pin_check(verilog_file, lef_file, uses_3v3=True) + precheck.power_pin_check(verilog_file, lef_file, uses_vapwr=True) def test_missing_use_power(verilog_lef_missing_use_power: tuple[str, str]): @@ -712,7 +712,7 @@ def test_missing_use_power(verilog_lef_missing_use_power: tuple[str, str]): precheck.PrecheckFailure, match="VDPWR does not have a corresponding 'USE POWER ;'", ): - precheck.power_pin_check(verilog_file, lef_file, uses_3v3=False) + precheck.power_pin_check(verilog_file, lef_file, uses_vapwr=False) def test_missing_use_ground(verilog_lef_missing_use_ground: tuple[str, str]): @@ -721,7 +721,7 @@ def test_missing_use_ground(verilog_lef_missing_use_ground: tuple[str, str]): precheck.PrecheckFailure, match="VGND does not have a corresponding 'USE GROUND ;'", ): - precheck.power_pin_check(verilog_file, lef_file, uses_3v3=False) + precheck.power_pin_check(verilog_file, lef_file, uses_vapwr=False) def test_invalid_layer(gds_invalid_layer: str): diff --git a/project.py b/project.py index 1f637fe..6854e21 100644 --- a/project.py +++ b/project.py @@ -203,7 +203,7 @@ class Project: [("input", "inout"), "VGND", 1], [("input", "inout"), "VDPWR", 1], ] - if self.info.uses_3v3: + if self.info.uses_vapwr: required_ports += [ [("input", "inout"), "VAPWR", 1], ] @@ -653,7 +653,7 @@ class Project: for i, desc in enumerate(self.info.pinout.ua) ], "is_analog": self.info.is_analog, - "uses_3v3": self.info.uses_3v3, + "uses_vapwr": self.info.uses_vapwr, } ) diff --git a/project_info.py b/project_info.py index c886a04..1d78d53 100644 --- a/project_info.py +++ b/project_info.py @@ -131,10 +131,13 @@ class ProjectInfo: self.analog_pins: int = analog_pins self.is_analog: bool = self.analog_pins > 0 - uses_3v3: bool = project_section.get("uses_3v3", False) - self.uses_3v3: bool = uses_3v3 - if uses_3v3 and not self.is_analog: - errors.append("Projects with 3v3 power need at least one analog pin") + # "uses_3v3" is the legacy name for "uses_vapwr"; still accepted for compat. + uses_vapwr: bool = project_section.get( + "uses_vapwr", project_section.get("uses_3v3", False) + ) + self.uses_vapwr: bool = uses_vapwr + if uses_vapwr and not self.is_analog: + errors.append("Projects with VAPWR power need at least one analog pin") language = project_section.get("language") if language is None: diff --git a/shuttle.py b/shuttle.py index 21df574..d341f58 100644 --- a/shuttle.py +++ b/shuttle.py @@ -101,7 +101,7 @@ class ShuttleConfig: "width": width, "height": height, "analog": {i: None for i in range(project.info.analog_pins)}, - "pg_vaa": project.info.uses_3v3, + "pg_vaa": project.info.uses_vapwr, } module_config["modules"].append(module_entry) if self.config.get("no_power_gating", False): diff --git a/test_project_info.py b/test_project_info.py index 58bdb64..b199948 100644 --- a/test_project_info.py +++ b/test_project_info.py @@ -15,7 +15,7 @@ def valid_yaml_data(): "description": "Test Description", "tiles": "1x1", "analog_pins": 0, - "uses_3v3": False, + "uses_vapwr": False, "language": "Verilog", "top_module": "tt_um_test_project", "source_files": ["test.v"], @@ -167,12 +167,12 @@ class TestProjectInfoProjectSection: ): ProjectInfo(valid_yaml_data, tile_sizes) - def test_uses_3v3_without_analog_pins(self, valid_yaml_data, tile_sizes): - valid_yaml_data["project"]["uses_3v3"] = True + def test_uses_vapwr_without_analog_pins(self, valid_yaml_data, tile_sizes): + valid_yaml_data["project"]["uses_vapwr"] = True valid_yaml_data["project"]["analog_pins"] = 0 with pytest.raises( ProjectYamlError, - match="Projects with 3v3 power need at least one analog pin", + match="Projects with VAPWR power need at least one analog pin", ): ProjectInfo(valid_yaml_data, tile_sizes) @@ -375,7 +375,7 @@ class TestProjectInfoValidCombinations: def test_valid_analog_project(self, valid_yaml_data, tile_sizes): valid_yaml_data["project"]["analog_pins"] = 2 - valid_yaml_data["project"]["uses_3v3"] = True + valid_yaml_data["project"]["uses_vapwr"] = True # Include all required ua pins for i in range(6): valid_yaml_data["pinout"][f"ua[{i}]"] = f"analog_{i}" if i < 2 else "" @@ -383,13 +383,24 @@ class TestProjectInfoValidCombinations: project_info = ProjectInfo(valid_yaml_data, tile_sizes) assert project_info.analog_pins == 2 assert project_info.is_analog is True - assert project_info.uses_3v3 is True + assert project_info.uses_vapwr is True + + def test_uses_vapwr_legacy_uses_3v3_alias(self, valid_yaml_data, tile_sizes): + # The legacy "uses_3v3" key is still accepted as an alias for uses_vapwr. + valid_yaml_data["project"]["analog_pins"] = 2 + del valid_yaml_data["project"]["uses_vapwr"] + valid_yaml_data["project"]["uses_3v3"] = True + for i in range(6): + valid_yaml_data["pinout"][f"ua[{i}]"] = f"analog_{i}" if i < 2 else "" + + project_info = ProjectInfo(valid_yaml_data, tile_sizes) + assert project_info.uses_vapwr is True def test_valid_digital_project(self, valid_yaml_data, tile_sizes): project_info = ProjectInfo(valid_yaml_data, tile_sizes) assert project_info.analog_pins == 0 assert project_info.is_analog is False - assert project_info.uses_3v3 is False + assert project_info.uses_vapwr is False def test_optional_fields(self, valid_yaml_data, tile_sizes): # Test that optional fields work @@ -406,11 +417,11 @@ class TestProjectInfoValidCombinations: project_info = ProjectInfo(valid_yaml_data, tile_sizes) assert project_info.analog_pins == 0 - def test_default_uses_3v3(self, valid_yaml_data, tile_sizes): - # Test that uses_3v3 defaults to False when not specified - del valid_yaml_data["project"]["uses_3v3"] + def test_default_uses_vapwr(self, valid_yaml_data, tile_sizes): + # Test that uses_vapwr defaults to False when not specified + del valid_yaml_data["project"]["uses_vapwr"] project_info = ProjectInfo(valid_yaml_data, tile_sizes) - assert project_info.uses_3v3 is False + assert project_info.uses_vapwr is False def test_all_tile_sizes(self, valid_yaml_data, tile_sizes): # Test all valid tile sizes