feat(tt_tool): --open-in-openroad and --open-in-klayout flags #113

close #113

project.py

@@ -603,6 +603,15 @@ class Project:
             os.path.join(stats_dir, "synthesis-stats.txt"),
         )
 
+    def run_custom_librelane_flow(self, flow_name: str):
+        logging.info(f"Running {flow_name} for {self}")
+        ll_cmd = f"python -m librelane --docker-no-tty --dockerized {self.tech.librelane_pdk_args} --run-tag wokwi --force-run-dir {self.local_dir}/runs/wokwi {self.local_dir}/src/config_merged.json --flow {flow_name}"
+        logging.debug(ll_cmd)
+        p = subprocess.run(ll_cmd, shell=True)
+        if p.returncode != 0:
+            logging.error("librelane failed")
+            exit(1)
+
     def create_fpga_bitstream(self, args):
         logging.info(f"Creating FPGA bitstream for {self}")
 

tt_tool.py

@@ -117,6 +117,18 @@ if __name__ == "__main__":
         action="store_const",
         const=True,
     )
+    parser.add_argument(
+        "--open-in-klayout",
+        help="open the hardened design in KLayout",
+        action="store_const",
+        const=True,
+    )
+    parser.add_argument(
+        "--open-in-openroad",
+        help="open the hardened design in OpenROAD",
+        action="store_const",
+        const=True,
+    )
 
     # FPGA
     parser.add_argument(
@@ -189,6 +201,12 @@ if __name__ == "__main__":
     if args.create_tt_submission:
         project.create_tt_submission()
 
+    if args.open_in_klayout:
+        project.run_custom_librelane_flow("OpenInKLayout")
+
+    if args.open_in_openroad:
+        project.run_custom_librelane_flow("OpenInOpenROAD")
+
     if args.create_pdf:
         project.create_pdf()