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feat(precheck): add Verilog syntax check

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htfab
2026-03-26 13:05:34 +01:00
parent bd4a4a08e5
commit 201d0273dc
4 changed files with 74 additions and 1 deletions
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precheck/pyproject.toml
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@@ -8,6 +8,7 @@ dependencies = [
"numpy<2",
"pytest",
"PyYAML",
"yowasp-yosys",
]
[tool.setuptools]