feat(precheck): add Verilog syntax check

This commit is contained in:
htfab
2026-03-26 13:05:34 +01:00
parent bd4a4a08e5
commit 201d0273dc
4 changed files with 74 additions and 1 deletions
+11 -1
View File
@@ -1,9 +1,11 @@
#
# This file is autogenerated by pip-compile with Python 3.12
# This file is autogenerated by pip-compile with Python 3.13
# by the following command:
#
# pip-compile
#
click==8.3.1
# via yowasp-yosys
gdstk==0.9.52
# via tt-precheck (pyproject.toml)
iniconfig==2.0.0
@@ -16,9 +18,17 @@ numpy==1.26.4
# tt-precheck (pyproject.toml)
packaging==24.1
# via pytest
platformdirs==4.9.4
# via yowasp-runtime
pluggy==1.5.0
# via pytest
pytest==8.2.2
# via tt-precheck (pyproject.toml)
pyyaml==6.0.1
# via tt-precheck (pyproject.toml)
wasmtime==42.0.0
# via yowasp-runtime
yowasp-runtime==1.88
# via yowasp-yosys
yowasp-yosys==0.63.0.0.post1107
# via tt-precheck (pyproject.toml)