mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
feat(precheck): add Verilog syntax check
This commit is contained in:
@@ -1,9 +1,11 @@
|
||||
#
|
||||
# This file is autogenerated by pip-compile with Python 3.12
|
||||
# This file is autogenerated by pip-compile with Python 3.13
|
||||
# by the following command:
|
||||
#
|
||||
# pip-compile
|
||||
#
|
||||
click==8.3.1
|
||||
# via yowasp-yosys
|
||||
gdstk==0.9.52
|
||||
# via tt-precheck (pyproject.toml)
|
||||
iniconfig==2.0.0
|
||||
@@ -16,9 +18,17 @@ numpy==1.26.4
|
||||
# tt-precheck (pyproject.toml)
|
||||
packaging==24.1
|
||||
# via pytest
|
||||
platformdirs==4.9.4
|
||||
# via yowasp-runtime
|
||||
pluggy==1.5.0
|
||||
# via pytest
|
||||
pytest==8.2.2
|
||||
# via tt-precheck (pyproject.toml)
|
||||
pyyaml==6.0.1
|
||||
# via tt-precheck (pyproject.toml)
|
||||
wasmtime==42.0.0
|
||||
# via yowasp-runtime
|
||||
yowasp-runtime==1.88
|
||||
# via yowasp-yosys
|
||||
yowasp-yosys==0.63.0.0.post1107
|
||||
# via tt-precheck (pyproject.toml)
|
||||
|
||||
Reference in New Issue
Block a user