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feat(precheck): add extra prechecks

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- no shapes outside project area
- VPWR/VGND present, VAPWR present iff uses_3v3
- no invalid layers
- cell names don't have '#' or '/'
- urpm to nwell spacing satisfies DRC
- analog pins have adjacent metal iff marked as used
This commit is contained in:
htfab
2025-01-31 17:53:57 +02:00
committed by Uri Shaked
parent 2036138b0e
commit 2241597d6b
6 changed files with 500 additions and 62 deletions
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precheck/reports/.gitignore
+1
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@@ -3,6 +3,7 @@ drc_feol.xml
drc_offgrid.xml
drc_pin_label_purposes_overlapping_drawing.xml
drc_zero_area.xml
drc_nwell_urpm.xml
magic_drc.mag
magic_drc.txt
results.md