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feat(precheck): add extra prechecks
- no shapes outside project area - VPWR/VGND present, VAPWR present iff uses_3v3 - no invalid layers - cell names don't have '#' or '/' - urpm to nwell spacing satisfies DRC - analog pins have adjacent metal iff marked as used
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@@ -1,3 +1,4 @@
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sky130A_mr.drc from https://github.com/efabless/mpw_precheck revision 3467a4c8252aa884cddc7d3f73370df9744dd65e
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pin_label_purposes_overlapping_drawing.rb.drc from https://github.com/efabless/mpw_precheck revision f6b9c3d3f00694f96dce8444149449b4719180f0
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zeroarea.rb.drc from https://github.com/efabless/mpw_precheck revision 4fd5283b124e931c9e71219f47270075176f84e2
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nwell_urpm.drc from https://open-source-silicon.slack.com/archives/C05FW1VMY5A/p1729112262642699?thread_ts=1728921677.220509&cid=C05FW1VMY5A
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@@ -0,0 +1,14 @@
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source($input, $top_cell)
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report("SKY130 DRC runset", $report)
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deep
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threads($thr)
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verbose(true)
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nwell = polygons(64, 20)
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urpm = polygons(79, 20)
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nwell.separation(urpm,0.7, euclidian).output(
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"nwell space to urpm",
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"nwell space to urpm: min. nwell spacing to urpm 0.7um"
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)
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