mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
feat(precheck): add extra prechecks
- no shapes outside project area - VPWR/VGND present, VAPWR present iff uses_3v3 - no invalid layers - cell names don't have '#' or '/' - urpm to nwell spacing satisfies DRC - analog pins have adjacent metal iff marked as used
This commit is contained in:
htfab
+237
-10
@@ -107,6 +107,114 @@ def gds_invalid_macro_name(tmp_path_factory: pytest.TempPathFactory):
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return str(gds_file)
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@pytest.fixture(scope="session")
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def gds_shapes_outside_area(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS with shapes outside the project area."""
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_shapes_outside_area.gds"
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layout = pya.Layout()
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met1_info = gds_layers["met1.drawing"]
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met1 = layout.layer(met1_info.layer, met1_info.data_type)
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top_cell = layout.create_cell("TEST_shapes_outside_area")
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rect = pya.DBox(-1, 0, 0, 1)
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top_cell.shapes(met1).insert(rect)
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layout.write(str(gds_file))
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return str(gds_file)
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@pytest.fixture(scope="session")
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def verilog_lef_wrong_power_pins(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a Verilog & LEF file with wrong power pins."""
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verilog_file = tmp_path_factory.mktemp("verilog") / "TEST_wrong_power_pins.v"
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verilog_data = """
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`default_nettype none
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module TEST_wrong_power_pins (
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input wire VGND,
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input wire VDPWR,
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input wire VAPWR
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);
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endmodule
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"""
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open(verilog_file, "w").write(textwrap.dedent(verilog_data))
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lef_file = tmp_path_factory.mktemp("lef") / "TEST_wrong_power_pins.lef"
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lef_data = """
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VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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MACRO TEST_wrong_power_pins
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CLASS BLOCK ;
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FOREIGN TEST_wrong_power_pins ;
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ORIGIN 0.000 0.000 ;
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SIZE 161.000 BY 111.520 ;
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PIN VGND
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DIRECTION INOUT ;
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 21.580 2.480 23.180 109.040 ;
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END
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END VGND
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PIN VDPWR
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DIRECTION INOUT ;
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 18.280 2.480 19.880 109.040 ;
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END
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END VDPWR
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"""
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open(lef_file, "w").write(textwrap.dedent(lef_data))
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return str(verilog_file), str(lef_file)
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@pytest.fixture(scope="session")
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def gds_invalid_layer(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS with a layer/datatype not defined in sky130."""
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_invalid_layer.gds"
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layout = pya.Layout()
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invalid_layer = layout.layer(255, 255)
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top_cell = layout.create_cell("TEST_invalid_layer")
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rect = pya.DBox(0, 0, 5, 5)
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top_cell.shapes(invalid_layer).insert(rect)
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layout.write(str(gds_file))
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return str(gds_file)
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@pytest.fixture(scope="session")
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def gds_invalid_cell_name(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS with a subcell having a '#' in its name."""
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_invalid_cell_name.gds"
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layout = pya.Layout()
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top_cell = layout.create_cell("TEST_invalid_cell_name")
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subcell = layout.create_cell("subcell#")
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subcell_instance = pya.CellInstArray(subcell, pya.Trans())
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top_cell.insert(subcell_instance)
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layout.write(str(gds_file))
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return str(gds_file)
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@pytest.fixture(scope="session")
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def gds_urpm_nwell_too_close(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS with a subcell having a '#' in its name."""
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_urpm_nwell_too_close.gds"
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layout = pya.Layout()
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nwell_info = gds_layers["nwell.drawing"]
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nwell = layout.layer(nwell_info.layer, nwell_info.data_type)
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urpm = layout.layer(79, 20)
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# Hardcoding "urpm" layer/datatype because the .lyp file on the PDK version
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# we use on GitHub Actions doesn't have it yet. Once we upgrade it, we can
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# replace the line above with:
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# urpm_info = gds_layers["urpm"]
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# urpm = layout.layer(urpm_info.layer, urpm_info.data_type)
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top_cell = layout.create_cell("TEST_urpm_nwell_too_close")
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nwell_rect = pya.DBox(0, 0, 5, 5)
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top_cell.shapes(nwell).insert(nwell_rect)
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urpm_rect = pya.DBox(5, 0, 10, 5)
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top_cell.shapes(urpm).insert(urpm_rect)
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layout.write(str(gds_file))
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return str(gds_file)
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class PortRect:
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def __init__(
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self, layer: str, bottom_left: tuple[int, int], top_right: tuple[int, int]
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@@ -153,17 +261,23 @@ def generate_analog_example(
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f"""
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box {rect.lx} {rect.by} {rect.rx} {rect.ty}
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paint {rect.layer}
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label {port.name} FreeSans {rect.layer}
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"""
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)
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tcl_append(
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f"""
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port {port.name} makeall n
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port {port.name} use {port.port_use}
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port {port.name} class {port.port_class}
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port conn n s e w
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"""
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)
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if port.name:
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tcl_append(
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f"""
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label {port.name} FreeSans {rect.layer}
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"""
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)
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if port.name:
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tcl_append(
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f"""
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port {port.name} makeall n
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port {port.name} use {port.port_use}
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port {port.name} class {port.port_class}
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port conn n s e w
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"""
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)
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tcl_append(
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f"""
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# Export
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@@ -294,7 +408,7 @@ def gds_lef_analog_compound_vgnd(tmp_path_factory: pytest.TempPathFactory):
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@pytest.fixture(scope="session")
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def gds_lef_analog_example_3v3(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS and LEF using the 1x2 analog template."""
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"""Creates a GDS and LEF using the 1x2 analog template using 3v3 power."""
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tcl_file = tmp_path_factory.mktemp("tcl") / "TEST_analog_example_3v3.tcl"
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_analog_example_3v3.gds"
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lef_file = tmp_path_factory.mktemp("lef") / "TEST_analog_example_3v3.lef"
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@@ -313,6 +427,28 @@ def gds_lef_analog_example_3v3(tmp_path_factory: pytest.TempPathFactory):
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return str(gds_file), str(lef_file)
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@pytest.fixture(scope="session")
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def gds_lef_analog_pin_example(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS and LEF using the 1x2 analog template with 2 analog pins used."""
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tcl_file = tmp_path_factory.mktemp("tcl") / "TEST_analog_pin_example.tcl"
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_analog_pin_example.gds"
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lef_file = tmp_path_factory.mktemp("lef") / "TEST_analog_pin_example.lef"
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generate_analog_example(
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str(tcl_file),
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str(gds_file),
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str(lef_file),
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"TEST_analog_example",
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[
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SimplePort("VDPWR", "met4", (100, 500), (250, 22076)),
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SimplePort("VGND", "met4", (4900, 500), (5050, 22076)),
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SimplePort("", "via3", (15200, 30), (15250, 80)),
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SimplePort("", "via3", (13270, 30), (13320, 80)),
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],
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)
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return str(gds_file), str(lef_file)
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def test_magic_drc_pass(gds_valid: str):
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precheck.magic_drc(gds_valid, "TEST_valid")
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@@ -376,6 +512,44 @@ def test_klayout_zero_area_drc_fail(gds_zero_area: str):
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precheck.klayout_zero_area(gds_zero_area)
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def test_shapes_outside_area(gds_shapes_outside_area: str):
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with pytest.raises(precheck.PrecheckFailure, match="Shapes outside project area"):
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precheck.boundary_check(gds_shapes_outside_area)
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def test_wrong_power_pins_1(verilog_lef_wrong_power_pins: tuple[str, str]):
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verilog_file, lef_file = verilog_lef_wrong_power_pins
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with pytest.raises(precheck.PrecheckFailure, match="Verilog contains VAPWR"):
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precheck.power_pin_check(verilog_file, lef_file, uses_3v3=False)
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def test_wrong_power_pins_2(verilog_lef_wrong_power_pins: tuple[str, str]):
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verilog_file, lef_file = verilog_lef_wrong_power_pins
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with pytest.raises(precheck.PrecheckFailure, match="LEF doesn't contain VAPWR"):
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precheck.power_pin_check(verilog_file, lef_file, uses_3v3=True)
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def test_invalid_layer(gds_invalid_layer: str):
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with pytest.raises(precheck.PrecheckFailure, match="Invalid layers in GDS"):
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precheck.layer_check(gds_invalid_layer, "sky130")
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def test_invalid_cell_name(gds_invalid_cell_name: str):
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with pytest.raises(
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precheck.PrecheckFailure,
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match="Cell name subcell# contains invalid character '#'",
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):
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precheck.cell_name_check(gds_invalid_cell_name)
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def test_urpm_nwell_too_close(gds_urpm_nwell_too_close: str):
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with pytest.raises(
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precheck.PrecheckFailure,
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match="Klayout nwell_urpm failed with 1 DRC violations",
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):
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precheck.urpm_nwell_check(gds_urpm_nwell_too_close, "TEST_urpm_nwell_too_close")
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def test_pin_analog_example(gds_lef_analog_example: tuple[str, str]):
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gds_file, lef_file = gds_lef_analog_example
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precheck.pin_check(
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@@ -478,3 +652,56 @@ def test_pin_analog_3v3_mismatch2(gds_lef_analog_example_3v3: tuple[str, str]):
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"TEST_analog_example_3v3",
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False,
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)
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def test_analog_exact_pins(gds_lef_analog_pin_example: tuple[str, str]):
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gds_file, lef_file = gds_lef_analog_pin_example
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precheck.analog_pin_check(
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gds_file, "sky130", True, False, 2, {"ua[0]": "x", "ua[1]": "x"}
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)
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def test_analog_less_pins(gds_lef_analog_pin_example: tuple[str, str]):
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gds_file, lef_file = gds_lef_analog_pin_example
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with pytest.raises(
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precheck.PrecheckFailure, match="Analog pin 1 connected but `analog_pins` is 1"
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):
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precheck.analog_pin_check(
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gds_file, "sky130", True, False, 1, {"ua[0]": "x", "ua[1]": "x"}
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)
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def test_analog_more_pins(gds_lef_analog_pin_example: tuple[str, str]):
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gds_file, lef_file = gds_lef_analog_pin_example
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with pytest.raises(
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precheck.PrecheckFailure,
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match="Analog pin 2 not connected but `analog_pins` is 3",
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):
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precheck.analog_pin_check(
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gds_file, "sky130", True, False, 3, {"ua[0]": "x", "ua[1]": "x"}
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)
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def test_analog_less_ua_entries(gds_lef_analog_pin_example: tuple[str, str]):
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gds_file, lef_file = gds_lef_analog_pin_example
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with pytest.raises(
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precheck.PrecheckFailure,
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match="Analog pin 1 connected but `pinout\\.ua\\[1\\]` is falsy",
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):
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precheck.analog_pin_check(gds_file, "sky130", True, False, 2, {"ua[0]": "x"})
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def test_analog_more_ua_entries(gds_lef_analog_pin_example: tuple[str, str]):
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gds_file, lef_file = gds_lef_analog_pin_example
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with pytest.raises(
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precheck.PrecheckFailure,
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match="Analog pin 2 not connected but `pinout\\.ua\\[2\\]` is truthy",
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):
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precheck.analog_pin_check(
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gds_file,
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"sky130",
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True,
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False,
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2,
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{"ua[0]": "x", "ua[1]": "x", "ua[2]": "x"},
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)
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