From 2278ea867ee20d53d316531128e6e91f714a2788 Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Tue, 27 Oct 2026 11:17:19 +0100 Subject: [PATCH] feat: add ihp-sg13cmos5l PDK alongside ihp-sg13g2 Based on work done in the ihp-sg13cmos5l branch --- .github/workflows/test-harden.yaml | 19 +- config.py | 1 + doc_utils.py | 2 + docs/typst/src/datasheet.typ | 1 + logo.py | 2 +- precheck/precheck.py | 17 +- precheck/reports/.gitignore | 1 + precheck/tech_data.py | 34 +- rom/config.json | 6 + tech.py | 46 +- tech/ihp-sg13cmos5l/categories.json | 70 +++ tech/ihp-sg13cmos5l/cells.json | 247 ++++++++++ .../ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def | 281 ++++++++++++ .../ihp-sg13cmos5l/def/tt_block_1x2_pgvdd.def | 323 +++++++++++++ .../ihp-sg13cmos5l/def/tt_block_2x2_pgvdd.def | 323 +++++++++++++ .../ihp-sg13cmos5l/def/tt_block_3x2_pgvdd.def | 323 +++++++++++++ .../ihp-sg13cmos5l/def/tt_block_3x4_pgvdd.def | 428 ++++++++++++++++++ .../ihp-sg13cmos5l/def/tt_block_4x2_pgvdd.def | 323 +++++++++++++ .../ihp-sg13cmos5l/def/tt_block_4x4_pgvdd.def | 428 ++++++++++++++++++ .../ihp-sg13cmos5l/def/tt_block_5x4_pgvdd.def | 428 ++++++++++++++++++ .../ihp-sg13cmos5l/def/tt_block_6x2_pgvdd.def | 323 +++++++++++++ .../ihp-sg13cmos5l/def/tt_block_6x4_pgvdd.def | 428 ++++++++++++++++++ .../ihp-sg13cmos5l/def/tt_block_8x2_pgvdd.def | 323 +++++++++++++ .../ihp-sg13cmos5l/def/tt_block_8x4_pgvdd.def | 428 ++++++++++++++++++ tech/ihp-sg13cmos5l/tile_sizes.yaml | 17 + tech/ihp-sg13cmos5l/tt_logo_corner.gds | Bin 0 -> 16638 bytes tech/ihp-sg13cmos5l/tt_logo_corner.lef | 272 +++++++++++ tech/ihp-sg13cmos5l/tt_logo_corner.v | 4 + tt_tool.py | 13 +- 29 files changed, 5086 insertions(+), 25 deletions(-) create mode 100644 tech/ihp-sg13cmos5l/categories.json create mode 100644 tech/ihp-sg13cmos5l/cells.json create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_1x2_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_2x2_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_3x2_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_3x4_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_4x2_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_4x4_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_5x4_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_6x2_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_6x4_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_8x2_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/def/tt_block_8x4_pgvdd.def create mode 100644 tech/ihp-sg13cmos5l/tile_sizes.yaml create mode 100644 tech/ihp-sg13cmos5l/tt_logo_corner.gds create mode 100644 tech/ihp-sg13cmos5l/tt_logo_corner.lef create mode 100644 tech/ihp-sg13cmos5l/tt_logo_corner.v diff --git a/.github/workflows/test-harden.yaml b/.github/workflows/test-harden.yaml index 5907ffd..cb19bd8 100644 --- a/.github/workflows/test-harden.yaml +++ b/.github/workflows/test-harden.yaml @@ -10,7 +10,7 @@ jobs: strategy: fail-fast: false matrix: - pdk: [sky130A, ihp-sg13g2, gf180mcuD] + pdk: [sky130A, ihp-sg13g2, ihp-sg13cmos5l, gf180mcuD] runs-on: ubuntu-24.04 @@ -18,7 +18,8 @@ jobs: PDK: ${{ matrix.pdk }} PDK_ROOT: /home/runner/pdk PROJECT_DIR: /home/runner/project - LIBRELANE_VERSION: '3.0.2' + LIBRELANE_VERSION: '3.1.0.dev4' + TT_TOOL_ARGS: --pdk ${{ matrix.pdk }} steps: - name: Check out code @@ -37,20 +38,16 @@ jobs: run: pip install librelane==${LIBRELANE_VERSION} - name: Clone the factory test - if: "${{ matrix.pdk != 'ihp-sg13g2' }}" + if: "${{ matrix.pdk != 'ihp-sg13g2' && matrix.pdk != 'ihp-sg13cmos5l' }}" run: git clone https://github.com/tinytapeout/ttsky25a-factory-test ${PROJECT_DIR} - name: Clone the factory test (ihp-sg13g2) if: "${{ matrix.pdk == 'ihp-sg13g2' }}" run: git clone https://github.com/TinyTapeout/ttihp25b-factory-test ${PROJECT_DIR} - - name: Configure tt_tool.py args (IHP) - if: "${{ matrix.pdk == 'ihp-sg13g2' }}" - run: echo "TT_TOOL_ARGS=--ihp" >> $GITHUB_ENV - - - name: Configure tt_tool.py args (gf180mcuD) - if: "${{ matrix.pdk == 'gf180mcuD' }}" - run: echo "TT_TOOL_ARGS=--gf" >> $GITHUB_ENV + - name: Clone the factory test (ihp-sg13cmos5l) + if: "${{ matrix.pdk == 'ihp-sg13cmos5l' }}" + run: git clone https://github.com/TinyTapeout/ttihp0p4-factory-test ${PROJECT_DIR} - name: Copy tt-support-tools to the project directory run: cp -r . ${PROJECT_DIR}/tt @@ -94,5 +91,3 @@ jobs: with: name: svg-render-${{ matrix.pdk }} path: ${{ env.PROJECT_DIR }}/gds_render.svg - - \ No newline at end of file diff --git a/config.py b/config.py index 8ebc58b..039b885 100644 --- a/config.py +++ b/config.py @@ -18,6 +18,7 @@ class DatasheetConfig(TypedDict): "openframe", "openframe_sky130", "customframe_ihp_sg13g2", + "customframe_ihp_sg13cmos5l", "customframe_gf180mcud", ] theme_override_colour: str diff --git a/doc_utils.py b/doc_utils.py index 6b9018b..c582a71 100644 --- a/doc_utils.py +++ b/doc_utils.py @@ -437,6 +437,8 @@ class DocsHelper: content["pinout"] = "openframe_sky130" case "ihp-sg13g2": content["pinout"] = "customframe_ihp_sg13g2" + case "ihp-sg13cmos5l": + content["pinout"] = "customframe_ihp_sg13cmos5l" case "gf180mcuD": content["pinout"] = "customframe_gf180mcud" case _: diff --git a/docs/typst/src/datasheet.typ b/docs/typst/src/datasheet.typ index b9b1712..34d86ae 100644 --- a/docs/typst/src/datasheet.typ +++ b/docs/typst/src/datasheet.typ @@ -484,6 +484,7 @@ openframe: (diagram: "chip_pinout_qfn64", table: pins.openframe), openframe_sky130: (diagram: "chip_pinout_qfn64_sky130_openframe", table: pins.openframe_sky130), customframe_ihp_sg13g2: (diagram: "chip_pinout_qfn64_ihp_sg13g2", table: pins.customframe_ihp_sg13g2), + customframe_ihp_sg13cmos5l: (diagram: "chip_pinout_qfn64_ihp_sg13g2", table: pins.customframe_ihp_sg13g2), customframe_gf180mcud: (diagram: "chip_pinout_qfn64_gf180mcud", table: pins.customframe_gf180mcud) ) diff --git a/logo.py b/logo.py index ac6aa57..5936cad 100755 --- a/logo.py +++ b/logo.py @@ -119,7 +119,7 @@ if __name__ == "__main__": "--pdk", type=str, default="sky130A", - choices=["sky130A", "ihp-sg13g2", "gf180mcuD"], + choices=["sky130A", "ihp-sg13g2", "ihp-sg13cmos5l", "gf180mcuD"], ) parser.add_argument("--top", action="store_true") parser.add_argument("--bottom", action="store_true") diff --git a/precheck/precheck.py b/precheck/precheck.py index 104ce87..b1677b4 100644 --- a/precheck/precheck.py +++ b/precheck/precheck.py @@ -129,6 +129,14 @@ def klayout_sg13g2(gds: str): ) +def klayout_sg13cmos5l(gds: str): + return klayout_drc( + gds, + "sg13cmos5l", + f"{PDK_ROOT}/{PDK_NAME}/libs.tech/klayout/tech/drc/ihp-sg13cmos5l.drc", + ) + + def klayout_gf180mcuD_rule_deck(gds: str, top_module: str, check: str, decks: str): # All gf180mcuD DRC runs go through the PDK's unified rule deck # (gf180mcu.drc); `decks` selects which rule groups to run (see its @@ -452,6 +460,8 @@ def main(): pinout = yaml_data.get("pinout", {}) if uses_vapwr and not is_analog: raise PrecheckFailure("Projects with VAPWR power need at least one analog pin") + if is_analog and tech == "ihp-sg13cmos5l": + raise PrecheckFailure("Analog projects are not supported on ihp-sg13cmos5l yet") def_root = f"../tech/{tech}/def" if is_analog: analog_def = f"{def_root}/analog/tt_analog_{tiles}" @@ -463,7 +473,7 @@ def main(): template_def = f"{analog_def}_3v3.def" else: template_def = f"{analog_def}.def" - elif tech == "ihp-sg13g2" or tech == "gf180mcuD": + elif tech in ("ihp-sg13g2", "ihp-sg13cmos5l", "gf180mcuD"): template_def = f"{def_root}/tt_block_{tiles}_pgvdd.def" else: template_def = f"{def_root}/tt_block_{tiles}_pg.def" @@ -512,6 +522,11 @@ def main(): "check": lambda: klayout_sg13g2(gds_file), "techs": ["ihp-sg13g2"], }, + { + "name": "KLayout SG13CMOS5L DRC", + "check": lambda: klayout_sg13cmos5l(gds_file), + "techs": ["ihp-sg13cmos5l"], + }, {"name": "KLayout zero area", "check": lambda: klayout_zero_area(gds_file)}, { "name": "KLayout Checks", diff --git a/precheck/reports/.gitignore b/precheck/reports/.gitignore index e791120..7f904ec 100644 --- a/precheck/reports/.gitignore +++ b/precheck/reports/.gitignore @@ -5,6 +5,7 @@ drc_pin_label_purposes_overlapping_drawing.xml drc_zero_area.xml drc_nwell_urpm.xml drc_sg13g2.xml +drc_sg13cmos5l.xml drc_antenna.xml drc_gf180mcuD.xml magic_drc.mag diff --git a/precheck/tech_data.py b/precheck/tech_data.py index 64f9891..e54ade6 100644 --- a/precheck/tech_data.py +++ b/precheck/tech_data.py @@ -1,4 +1,4 @@ -tech_names = ["sky130A", "ihp-sg13g2", "gf180mcuD"] +tech_names = ["sky130A", "ihp-sg13g2", "ihp-sg13cmos5l", "gf180mcuD"] # fmt: off valid_layers_sky130A = [ @@ -78,6 +78,22 @@ valid_layers_ihp_sg13g2 = [ "isoNWell.drawing", ] +# Same as sg13g2, minus layers that don't exist in sg13cmos5l (nBuLay, MIM, Metal5, TopMetal2, ...) +# and minus TopMetal1, which is reserved for the chip-level power grid. +valid_layers_ihp_sg13cmos5l = [ + "Substrate.drawing", "Substrate.text", "Activ.drawing", "Activ.label", "Activ.nofill", "Activ.pin", "GatPoly.drawing", + "GatPoly.label", "GatPoly.nofill", "GatPoly.pin", "PolyRes.drawing", "PolyRes.label", "PolyRes.pin", "NWell.drawing", + "NWell.label", "NWell.pin", "PWell.block", "pSD.drawing", "nSD.drawing", "nSD.block", "SalBlock.drawing", + "ThickGateOx.drawing", "Cont.drawing", "Metal1.drawing", "Metal1.label", "Metal1.nofill", "Metal1.pin", "Metal1.slit", + "Metal1.text", "Metal1.res", "Via1.drawing", "Metal2.drawing", "Metal2.label", "Metal2.nofill", "Metal2.pin", + "Metal2.slit", "Metal2.text", "Metal2.res", "Via2.drawing", "Via2.net", "Via2.boundary", "Metal3.drawing", + "Metal3.label", "Metal3.nofill", "Metal3.pin", "Metal3.slit", "Metal3.text", "Metal3.res", "Via3.drawing", + "Metal4.drawing", "Metal4.label", "Metal4.nofill", "Metal4.pin", "Metal4.slit", "Metal4.text", "Metal4.res", + "TopMetal1.nofill", "TEXT.drawing", "Recog.drawing", "Recog.pin", "Recog.esd", "Recog.diode", "Recog.tsv", + "Recog.pdiode", "Recog.mom", "RES.drawing", "RES.label", "SRAM.drawing", "DigiBnd.drawing", "HeatRes.drawing", + "EXTBlock.drawing", "prBoundary.label", "prBoundary.boundary", +] + valid_layers_gf180mcuD = [ 'PR_bndry', 'pass_mk', 'fail_mk', 'polygon_mk', 'NAT', 'violation_mk', 'MCELL_FEOL_MK', 'MVPSD', 'rule_txt_mk', 'DNWELL', 'PROBE_MK', 'case_txt_mk', 'Nwell', 'COMP', 'COMP_Dummy', 'COMP_Label', 'ESD', 'ESD_MK', 'Poly2', @@ -139,11 +155,13 @@ def analog_pin_rects(tech: str, uses_vapwr: bool): valid_layers = { "sky130A": valid_layers_sky130A, "ihp-sg13g2": valid_layers_ihp_sg13g2, + "ihp-sg13cmos5l": valid_layers_ihp_sg13cmos5l, "gf180mcuD": valid_layers_gf180mcuD, } lyp_filename = { "sky130A": "sky130A.lyp", "ihp-sg13g2": "sg13g2.lyp", + "ihp-sg13cmos5l": "sg13cmos5l.lyp", "gf180mcuD": "gf180mcu.lyp", } @@ -163,6 +181,12 @@ valid_lef_port_layers = { "Metal5.pin": (67, 2), "TopMetal1.pin": (126, 2), }, + "ihp-sg13cmos5l": { + "Metal1.pin": (8, 2), + "Metal2.pin": (10, 2), + "Metal3.pin": (30, 2), + "Metal4.pin": (50, 2), + }, "gf180mcuD": { "Metal1_label": (34, 10), "Metal2_label": (36, 10), @@ -181,6 +205,11 @@ forbidden_layers = { "TopMetal2.pin", "TopMetal2.label", ], + "ihp-sg13cmos5l": [ + "TopMetal1.drawing", + "TopMetal1.pin", + "TopMetal1.label", + ], "gf180mcuD": [ "Metal5", "Metal5_Label", @@ -189,15 +218,18 @@ forbidden_layers = { power_pins_layer = { "sky130A": "met4", "ihp-sg13g2": "TopMetal1", + "ihp-sg13cmos5l": "Metal4", "gf180mcuD": "Metal4", } power_pins_min_width = { "sky130A": 1200, # 1.2 um "ihp-sg13g2": 2100, # 2.1 um + "ihp-sg13cmos5l": 2100, # 2.1 um "gf180mcuD": 800, # 0.8 um } boundary_layer = { "sky130A": "prBoundary.boundary", "ihp-sg13g2": "prBoundary.boundary", + "ihp-sg13cmos5l": "prBoundary.boundary", "gf180mcuD": "PR_bndry", } diff --git a/rom/config.json b/rom/config.json index d58ef2d..f6980e2 100644 --- a/rom/config.json +++ b/rom/config.json @@ -40,5 +40,11 @@ "DIE_AREA": [0, 0, 202.08, 154.98], "FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../tech/ihp-sg13g2/def/tt_block_1x1_pgvdd.def", "RT_MAX_LAYER": "Metal5" + }, + + "pdk::ihp-sg13cmos5l": { + "DIE_AREA": [0, 0, 202.08, 154.98], + "FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../tech/ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def", + "RT_MAX_LAYER": "Metal4" } } diff --git a/tech.py b/tech.py index 25dace3..de78b6e 100644 --- a/tech.py +++ b/tech.py @@ -2,7 +2,7 @@ import json import os from typing import Dict, List, Literal, Pattern, Protocol, Tuple, TypedDict, Union -TechName = Literal["sky130A", "ihp-sg13g2", "gf180mcuD", "fpgaUp5k"] +TechName = Literal["sky130A", "ihp-sg13g2", "ihp-sg13cmos5l", "gf180mcuD", "fpgaUp5k"] class CellDefinition(TypedDict): @@ -125,7 +125,9 @@ class Sky130Tech(Tech): return cells -class IHPTech(Tech): +class IHPG2Tech(Tech): + pdk_name = "ihp-sg13g2" + cell_doc_url = "https://raw.githubusercontent.com/IHP-GmbH/IHP-Open-PDK/refs/heads/main/ihp-sg13g2/libs.ref/sg13g2_stdcell/doc/sg13g2_stdcell_typ_1p20V_25C.pdf#{ref}" is_fpga = False def_suffix = "pgvdd" librelane_pdk_args = "--pdk ihp-sg13g2" @@ -166,19 +168,48 @@ class IHPTech(Tech): logo_pixel_size = 0.25 # um def read_pdk_version(self, pdk_root: str) -> PDKVersionInfo: - pdk_sources_file = os.path.join(pdk_root, "ihp-sg13g2", "SOURCES") + pdk_sources_file = os.path.join(pdk_root, self.pdk_name, "SOURCES") return parse_openpdks_pdk_version(pdk_sources_file, "IHP-Open-PDK") def load_cell_definitions(self) -> Dict[str, CellDefinition]: - URL_FORMAT = "https://raw.githubusercontent.com/IHP-GmbH/IHP-Open-PDK/refs/heads/main/ihp-sg13g2/libs.ref/sg13g2_stdcell/doc/sg13g2_stdcell_typ_1p20V_25C.pdf#{ref}" script_dir = os.path.dirname(os.path.realpath(__file__)) - with open(os.path.join(script_dir, "tech/ihp-sg13g2/cells.json")) as fh: + with open(os.path.join(script_dir, f"tech/{self.pdk_name}/cells.json")) as fh: cells = json.load(fh) for cell in cells.values(): - cell["url"] = URL_FORMAT.format(ref=cell["doc_ref"]) + cell["url"] = self.cell_doc_url.format(ref=cell["doc_ref"]) return cells +class IHPCmos5lTech(IHPG2Tech): + """ + SG13CMOS5L has five metal layers (Metal1-Metal4 + TopMetal1). Projects may + use up to Metal4, TopMetal1 is reserved for the chip-level power grid. + """ + + pdk_name = "ihp-sg13cmos5l" + # sg13cmos5l is only available on the dev branch of IHP-Open-PDK for now + cell_doc_url = "https://raw.githubusercontent.com/IHP-GmbH/IHP-Open-PDK/refs/heads/dev/ihp-sg13cmos5l/libs.ref/sg13cmos5l_stdcell/doc/sg13cmos5l_stdcell_typ_1p20V_25C.pdf#{ref}" + librelane_pdk_args = "--pdk ihp-sg13cmos5l" + cell_regexp = r"^\s*sg13cmos5l_(?P\S+)_(?P\d+)" + project_top_metal_layer = "Metal4" + label_layers = [ + (8, 1), # Metal1.label + (8, 25), # Metal1.text + (50, 25), # Metal4.text + (126, 25), # TopMetal1.text + ] + scramble_cells = "sg13cmos5l_" + mux_config_yaml_name = "ihp-sg13cmos5l.yaml" + mux_macros = [ + # No power gate macros yet, shuttles must set no_power_gating + ] + extra_logo_macros = [ + "tech/ihp-sg13cmos5l/tt_logo_corner", + ] + logo_layer = (50, 0) # Metal4.drawing + logo_layer_name = "Metal4" + + class GF180MCUDTech(Tech): is_fpga = False def_suffix = "pgvdd" @@ -277,7 +308,8 @@ class FpgaTech(Tech): tech_map: dict[TechName, Tech] = { - "ihp-sg13g2": IHPTech(), + "ihp-sg13g2": IHPG2Tech(), + "ihp-sg13cmos5l": IHPCmos5lTech(), "gf180mcuD": GF180MCUDTech(), "sky130A": Sky130Tech(), "fpgaUp5k": FpgaTech(), diff --git a/tech/ihp-sg13cmos5l/categories.json b/tech/ihp-sg13cmos5l/categories.json new file mode 100644 index 0000000..91547d3 --- /dev/null +++ b/tech/ihp-sg13cmos5l/categories.json @@ -0,0 +1,70 @@ +{ + "categories" : [ + "AND", + "OR", + "NAND", + "NOR", + "Clock", + "Flip Flops", + "Multiplexer", + "Latch", + "Inverter", + "Buffer", + "Fill", + "Tap", + "Diode", + "Combo Logic", + "Misc" + ], + "map" : { + "a21o" : 13, + "a21oi" : 13, + "a22oi" : 13, + "a221oi" : 13, + "and2" : 0, + "and3" : 0, + "and4" : 0, + "antennanp" : 12, + "buf" : 9, + "decap" : 10, + "dfrbp" : 5, + "dfrbpq": 5, + "dlhq" : 7, + "dlhr" : 7, + "dlhrq" : 7, + "dllr" : 7, + "dllrq" : 7, + "dlygate4sd1" : 14, + "dlygate4sd2" : 14, + "dlygate4sd3" : 14, + "ebufn" : 14, + "einvn" : 14, + "fill" : 10, + "inv" : 8, + "lgcp" : 4, + "mux2" : 6, + "mux4" : 6, + "nand2" : 2, + "nand2b" : 2, + "nand3" : 2, + "nand3b" : 2, + "nand4" : 2, + "nor2" : 3, + "nor2b" : 3, + "nor3" : 3, + "nor4" : 3, + "o21ai" : 13, + "or2" : 1, + "or3" : 1, + "or4" : 1, + "sdfbbp" : 5, + "sdfrbp" : 5, + "sdfrbpq" : 5, + "sighold" : 14, + "slgcp" : 4, + "tiehi" : 14, + "tielo" : 14, + "xnor2" : 3, + "xor2" : 1 + } +} diff --git a/tech/ihp-sg13cmos5l/cells.json b/tech/ihp-sg13cmos5l/cells.json new file mode 100644 index 0000000..bff1cee --- /dev/null +++ b/tech/ihp-sg13cmos5l/cells.json @@ -0,0 +1,247 @@ +{ + "a21o" : { + "description" : "2-input AND into first input of 2-input OR.", + "doc_name": "AO21x", + "doc_ref" : 7 + }, + "a21oi" : { + "description" : "2-input AND into first input of 2-input NOR.", + "doc_name": "A21OIx", + "doc_ref" : 1 + }, + "a221oi" : { + "description" : "2-input AND into first two inputs of 3-input NOR.", + "doc_name": "A221OI", + "doc_ref" : 2 + }, + "a22oi" : { + "description" : "2-input AND into both inputs of 2-input NOR.", + "doc_name": "A22OI", + "doc_ref" : 3 + }, + "and2" : { + "description" : "2-input AND.", + "doc_name": "AND2x", + "doc_ref" : 4 + }, + "and3" : { + "description" : "3-input AND.", + "doc_name": "AND3x", + "doc_ref" : 5 + }, + "and4" : { + "description" : "4-input AND.", + "doc_name": "AND4x", + "doc_ref" : 6 + }, + "antennanp" : { + "description" : "Antenna tie-down diode.", + "doc_name": "NP_ANT", + "doc_ref" : 38 + }, + "buf" : { + "description" : "Buffer.", + "doc_name": "BUx", + "doc_ref" : 9 + }, + "decap" : { + "description" : "Decoupling capacitance filler.", + "doc_name": "DECAPx", + "doc_ref" : 10 + }, + "dfrbp" : { + "description" : "Delay flop, inverted reset, complementary outputs.", + "doc_name": "DFFRRx", + "doc_ref" : 11 + }, + "dfrbpq": { + "description" : "Delay flop, inverted reset, single output.", + "doc_name": "DFRBPQx", + "doc_ref" : 0 + }, + "dlhq" : { + "description" : "Delay latch, non-inverted enable, single output.", + "doc_name": "DLHQ", + "doc_ref" : 12 + }, + "dlhr" : { + "description" : "Delay latch, inverted reset, non-inverted enable, complementary outputs.", + "doc_name": "DLHR", + "doc_ref" : 14 + }, + "dlhrq" : { + "description" : "Delay latch, inverted reset, non-inverted enable, single output.", + "doc_name": "DLHRQ", + "doc_ref" : 13 + }, + "dllr" : { + "description" : "Delay latch, inverted reset, inverted enable, complementary outputs.", + "doc_name": "DLLR", + "doc_ref" : 16 + }, + "dllrq" : { + "description" : "Delay latch, inverted reset, inverted enable, single output.", + "doc_name": "DLLRQ", + "doc_ref" : 15 + }, + "dlygate4sd1" : { + "description" : "Delay Buffer 4-stage ... length inner stage gates.", + "doc_name": "DLY1", + "doc_ref" : 17 + }, + "dlygate4sd2" : { + "description" : "Delay Buffer 4-stage ... length inner stage gates.", + "doc_name": "DLY2", + "doc_ref" : 18 + }, + "dlygate4sd3" : { + "description" : "Delay Buffer 4-stage ... length inner stage gates.", + "doc_name": "DLY4", + "doc_ref" : 19 + }, + "ebufn" : { + "description" : "Tri-state buffer, negative enable.", + "doc_name": "BTLx", + "doc_ref" : 8 + }, + "einvn" : { + "description" : "Tri-state inverter, negative enable.", + "doc_name": "EINVINx, ITL", + "doc_ref" : 20 + }, + "fill" : { + "description" : "Fill cell.", + "doc_name": "FILLx", + "doc_ref" : 21 + }, + "inv" : { + "description" : "Inverter.", + "doc_name": "INx", + "doc_ref" : 23 + }, + "lgcp" : { + "description" : "Clock gate.", + "doc_name": "GCLK", + "doc_ref" : 22 + }, + "mux2" : { + "description" : "2-input multiplexer.", + "doc_name": "MUX2x", + "doc_ref" : 26 + }, + "mux4" : { + "description" : "4-input multiplexer.", + "doc_name": "MUX4", + "doc_ref" : 27 + }, + "nand2" : { + "description" : "2-input NAND.", + "doc_name": "NAND2x", + "doc_ref" : 30 + }, + "nand2b" : { + "description" : "2-input NAND, first input inverted.", + "doc_name": "NAND2B1, NAND2B2", + "doc_ref" : 28 + }, + "nand3" : { + "description" : "3-input NAND.", + "doc_name": "NAND3", + "doc_ref" : 32 + }, + "nand3b" : { + "description" : "3-input NAND, first input inverted.", + "doc_name": "NAND3B1", + "doc_ref" : 31 + }, + "nand4" : { + "description" : "4-input NAND.", + "doc_name": "NAND4", + "doc_ref" : 33 + }, + "nor2" : { + "description" : "2-input NOR.", + "doc_name": "NOR2x", + "doc_ref" : 35 + }, + "nor2b" : { + "description" : "2-input NOR, first input inverted.", + "doc_name": "NOR2Bx", + "doc_ref" : 34 + }, + "nor3" : { + "description" : "3-input NOR.", + "doc_name": "NOR3x", + "doc_ref" : 36 + }, + "nor4" : { + "description" : "4-input NOR.", + "doc_name": "NOR4x", + "doc_ref" : 37 + }, + "o21ai" : { + "description" : "2-input OR into first input of 2-input NAND.", + "doc_name": "O21AI", + "doc_ref" : 39 + }, + "or2" : { + "description" : "2-input OR.", + "doc_name": "OR2x", + "doc_ref" : 40 + }, + "or3" : { + "description" : "3-input OR.", + "doc_name": "OR3x", + "doc_ref" : 41 + }, + "or4" : { + "description" : "4-input OR.", + "doc_name": "OR4x", + "doc_ref" : 42 + }, + "sdfbbp" : { + "description" : "Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.", + "doc_name": "SDFRRS", + "doc_ref" : 43 + }, + "sdfrbp": { + "description" : "Scan delay flop, inverted reset, non-inverted clock, complementary outputs.", + "doc_name": "SDFRBPx", + "doc_ref" : 0 + }, + "sdfrbpq": { + "description" : "Scan delay flop, inverted reset, non-inverted clock, single output.", + "doc_name": "SDFRBPQx", + "doc_ref" : 0 + }, + "sighold" : { + "description" : "Cross-coupled inverters.", + "doc_name": "KEEPSTATE", + "doc_ref" : 25 + }, + "slgcp" : { + "description" : "Scan gated clock.", + "doc_name": "SGCLK", + "doc_ref" : 44 + }, + "tiehi" : { + "description" : "Constant high output.", + "doc_name": "TIE1", + "doc_ref" : 46 + }, + "tielo" : { + "description" : "Constant low output.", + "doc_name": "TIE0", + "doc_ref" : 45 + }, + "xnor2" : { + "description" : "2-input exclusive NOR.", + "doc_name": "XNOR2_1", + "doc_ref" : 47 + }, + "xor2" : { + "description" : "2-input exclusive OR.", + "doc_name": "XOR2_1", + "doc_ref" : 48 + } +} diff --git a/tech/ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def new file mode 100644 index 0000000..81fad7b --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def @@ -0,0 +1,281 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 202080 154980 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 409 BY 1 STEP 480 0 ; +TRACKS X 480 DO 420 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 420 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 420 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 88 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 67 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 154480 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 154480 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 154480 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 154480 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 154480 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 154480 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 154480 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 154480 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 154480 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 154480 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 154480 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 154480 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 154480 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 154480 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 154480 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 154480 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 154480 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 154480 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 154480 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 154480 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 154480 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 154480 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 154480 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 154480 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 154480 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 154480 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 154480 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 154480 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 154480 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 154480 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 154480 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 154480 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 154480 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 154480 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 154480 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 154480 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 154480 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 154480 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 154480 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 154480 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 154480 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 154480 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 154480 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_1x2_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_1x2_pgvdd.def new file mode 100644 index 0000000..e239144 --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_1x2_pgvdd.def @@ -0,0 +1,323 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 202080 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 409 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 409 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 409 BY 1 STEP 480 0 ; +TRACKS X 480 DO 420 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 420 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 420 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 88 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_2x2_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_2x2_pgvdd.def new file mode 100644 index 0000000..52ba81a --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_2x2_pgvdd.def @@ -0,0 +1,323 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 419520 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 862 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 862 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 862 BY 1 STEP 480 0 ; +TRACKS X 480 DO 873 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 873 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 873 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 873 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 183 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_3x2_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_3x2_pgvdd.def new file mode 100644 index 0000000..ea16597 --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_3x2_pgvdd.def @@ -0,0 +1,323 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 636960 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 1315 BY 1 STEP 480 0 ; +TRACKS X 480 DO 1326 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 1326 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 1326 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 1326 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 279 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_3x4_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_3x4_pgvdd.def new file mode 100644 index 0000000..08c8ce9 --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_3x4_pgvdd.def @@ -0,0 +1,428 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 636960 710640 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_81 CoreSite 2880 309960 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_82 CoreSite 2880 313740 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_83 CoreSite 2880 317520 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_84 CoreSite 2880 321300 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_85 CoreSite 2880 325080 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_86 CoreSite 2880 328860 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_87 CoreSite 2880 332640 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_88 CoreSite 2880 336420 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_89 CoreSite 2880 340200 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_90 CoreSite 2880 343980 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_91 CoreSite 2880 347760 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_92 CoreSite 2880 351540 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_93 CoreSite 2880 355320 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_94 CoreSite 2880 359100 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_95 CoreSite 2880 362880 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_96 CoreSite 2880 366660 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_97 CoreSite 2880 370440 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_98 CoreSite 2880 374220 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_99 CoreSite 2880 378000 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_100 CoreSite 2880 381780 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_101 CoreSite 2880 385560 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_102 CoreSite 2880 389340 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_103 CoreSite 2880 393120 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_104 CoreSite 2880 396900 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_105 CoreSite 2880 400680 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_106 CoreSite 2880 404460 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_107 CoreSite 2880 408240 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_108 CoreSite 2880 412020 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_109 CoreSite 2880 415800 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_110 CoreSite 2880 419580 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_111 CoreSite 2880 423360 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_112 CoreSite 2880 427140 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_113 CoreSite 2880 430920 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_114 CoreSite 2880 434700 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_115 CoreSite 2880 438480 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_116 CoreSite 2880 442260 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_117 CoreSite 2880 446040 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_118 CoreSite 2880 449820 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_119 CoreSite 2880 453600 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_120 CoreSite 2880 457380 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_121 CoreSite 2880 461160 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_122 CoreSite 2880 464940 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_123 CoreSite 2880 468720 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_124 CoreSite 2880 472500 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_125 CoreSite 2880 476280 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_126 CoreSite 2880 480060 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_127 CoreSite 2880 483840 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_128 CoreSite 2880 487620 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_129 CoreSite 2880 491400 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_130 CoreSite 2880 495180 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_131 CoreSite 2880 498960 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_132 CoreSite 2880 502740 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_133 CoreSite 2880 506520 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_134 CoreSite 2880 510300 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_135 CoreSite 2880 514080 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_136 CoreSite 2880 517860 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_137 CoreSite 2880 521640 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_138 CoreSite 2880 525420 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_139 CoreSite 2880 529200 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_140 CoreSite 2880 532980 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_141 CoreSite 2880 536760 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_142 CoreSite 2880 540540 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_143 CoreSite 2880 544320 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_144 CoreSite 2880 548100 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_145 CoreSite 2880 551880 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_146 CoreSite 2880 555660 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_147 CoreSite 2880 559440 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_148 CoreSite 2880 563220 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_149 CoreSite 2880 567000 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_150 CoreSite 2880 570780 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_151 CoreSite 2880 574560 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_152 CoreSite 2880 578340 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_153 CoreSite 2880 582120 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_154 CoreSite 2880 585900 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_155 CoreSite 2880 589680 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_156 CoreSite 2880 593460 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_157 CoreSite 2880 597240 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_158 CoreSite 2880 601020 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_159 CoreSite 2880 604800 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_160 CoreSite 2880 608580 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_161 CoreSite 2880 612360 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_162 CoreSite 2880 616140 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_163 CoreSite 2880 619920 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_164 CoreSite 2880 623700 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_165 CoreSite 2880 627480 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_166 CoreSite 2880 631260 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_167 CoreSite 2880 635040 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_168 CoreSite 2880 638820 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_169 CoreSite 2880 642600 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_170 CoreSite 2880 646380 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_171 CoreSite 2880 650160 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_172 CoreSite 2880 653940 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_173 CoreSite 2880 657720 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_174 CoreSite 2880 661500 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_175 CoreSite 2880 665280 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_176 CoreSite 2880 669060 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_177 CoreSite 2880 672840 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_178 CoreSite 2880 676620 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_179 CoreSite 2880 680400 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_180 CoreSite 2880 684180 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_181 CoreSite 2880 687960 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_182 CoreSite 2880 691740 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_183 CoreSite 2880 695520 FS DO 1315 BY 1 STEP 480 0 ; +ROW ROW_184 CoreSite 2880 699300 N DO 1315 BY 1 STEP 480 0 ; +ROW ROW_185 CoreSite 2880 703080 FS DO 1315 BY 1 STEP 480 0 ; +TRACKS X 480 DO 1326 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 1326 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 1326 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 1326 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 279 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 710140 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 710140 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 710140 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 710140 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 710140 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 710140 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 710140 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 710140 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 710140 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 710140 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 710140 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 710140 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 710140 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 710140 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 710140 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 710140 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 710140 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 710140 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 710140 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 710140 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 710140 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 710140 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 710140 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 710140 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 710140 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 710140 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 710140 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 710140 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 710140 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 710140 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 710140 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 710140 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 710140 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 710140 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 710140 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 710140 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 710140 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 710140 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 710140 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 710140 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 710140 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 710140 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 710140 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_4x2_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_4x2_pgvdd.def new file mode 100644 index 0000000..4667dd5 --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_4x2_pgvdd.def @@ -0,0 +1,323 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 854400 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 1768 BY 1 STEP 480 0 ; +TRACKS X 480 DO 1779 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 1779 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 1779 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 374 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_4x4_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_4x4_pgvdd.def new file mode 100644 index 0000000..04e582c --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_4x4_pgvdd.def @@ -0,0 +1,428 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 854400 710640 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_81 CoreSite 2880 309960 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_82 CoreSite 2880 313740 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_83 CoreSite 2880 317520 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_84 CoreSite 2880 321300 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_85 CoreSite 2880 325080 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_86 CoreSite 2880 328860 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_87 CoreSite 2880 332640 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_88 CoreSite 2880 336420 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_89 CoreSite 2880 340200 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_90 CoreSite 2880 343980 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_91 CoreSite 2880 347760 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_92 CoreSite 2880 351540 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_93 CoreSite 2880 355320 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_94 CoreSite 2880 359100 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_95 CoreSite 2880 362880 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_96 CoreSite 2880 366660 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_97 CoreSite 2880 370440 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_98 CoreSite 2880 374220 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_99 CoreSite 2880 378000 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_100 CoreSite 2880 381780 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_101 CoreSite 2880 385560 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_102 CoreSite 2880 389340 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_103 CoreSite 2880 393120 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_104 CoreSite 2880 396900 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_105 CoreSite 2880 400680 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_106 CoreSite 2880 404460 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_107 CoreSite 2880 408240 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_108 CoreSite 2880 412020 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_109 CoreSite 2880 415800 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_110 CoreSite 2880 419580 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_111 CoreSite 2880 423360 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_112 CoreSite 2880 427140 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_113 CoreSite 2880 430920 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_114 CoreSite 2880 434700 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_115 CoreSite 2880 438480 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_116 CoreSite 2880 442260 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_117 CoreSite 2880 446040 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_118 CoreSite 2880 449820 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_119 CoreSite 2880 453600 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_120 CoreSite 2880 457380 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_121 CoreSite 2880 461160 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_122 CoreSite 2880 464940 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_123 CoreSite 2880 468720 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_124 CoreSite 2880 472500 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_125 CoreSite 2880 476280 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_126 CoreSite 2880 480060 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_127 CoreSite 2880 483840 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_128 CoreSite 2880 487620 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_129 CoreSite 2880 491400 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_130 CoreSite 2880 495180 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_131 CoreSite 2880 498960 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_132 CoreSite 2880 502740 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_133 CoreSite 2880 506520 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_134 CoreSite 2880 510300 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_135 CoreSite 2880 514080 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_136 CoreSite 2880 517860 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_137 CoreSite 2880 521640 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_138 CoreSite 2880 525420 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_139 CoreSite 2880 529200 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_140 CoreSite 2880 532980 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_141 CoreSite 2880 536760 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_142 CoreSite 2880 540540 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_143 CoreSite 2880 544320 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_144 CoreSite 2880 548100 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_145 CoreSite 2880 551880 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_146 CoreSite 2880 555660 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_147 CoreSite 2880 559440 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_148 CoreSite 2880 563220 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_149 CoreSite 2880 567000 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_150 CoreSite 2880 570780 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_151 CoreSite 2880 574560 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_152 CoreSite 2880 578340 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_153 CoreSite 2880 582120 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_154 CoreSite 2880 585900 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_155 CoreSite 2880 589680 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_156 CoreSite 2880 593460 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_157 CoreSite 2880 597240 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_158 CoreSite 2880 601020 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_159 CoreSite 2880 604800 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_160 CoreSite 2880 608580 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_161 CoreSite 2880 612360 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_162 CoreSite 2880 616140 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_163 CoreSite 2880 619920 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_164 CoreSite 2880 623700 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_165 CoreSite 2880 627480 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_166 CoreSite 2880 631260 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_167 CoreSite 2880 635040 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_168 CoreSite 2880 638820 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_169 CoreSite 2880 642600 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_170 CoreSite 2880 646380 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_171 CoreSite 2880 650160 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_172 CoreSite 2880 653940 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_173 CoreSite 2880 657720 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_174 CoreSite 2880 661500 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_175 CoreSite 2880 665280 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_176 CoreSite 2880 669060 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_177 CoreSite 2880 672840 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_178 CoreSite 2880 676620 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_179 CoreSite 2880 680400 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_180 CoreSite 2880 684180 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_181 CoreSite 2880 687960 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_182 CoreSite 2880 691740 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_183 CoreSite 2880 695520 FS DO 1768 BY 1 STEP 480 0 ; +ROW ROW_184 CoreSite 2880 699300 N DO 1768 BY 1 STEP 480 0 ; +ROW ROW_185 CoreSite 2880 703080 FS DO 1768 BY 1 STEP 480 0 ; +TRACKS X 480 DO 1779 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 1779 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 1779 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 374 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 710140 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 710140 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 710140 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 710140 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 710140 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 710140 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 710140 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 710140 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 710140 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 710140 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 710140 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 710140 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 710140 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 710140 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 710140 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 710140 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 710140 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 710140 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 710140 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 710140 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 710140 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 710140 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 710140 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 710140 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 710140 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 710140 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 710140 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 710140 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 710140 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 710140 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 710140 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 710140 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 710140 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 710140 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 710140 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 710140 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 710140 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 710140 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 710140 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 710140 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 710140 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 710140 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 710140 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_5x4_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_5x4_pgvdd.def new file mode 100644 index 0000000..8fa7914 --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_5x4_pgvdd.def @@ -0,0 +1,428 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1071840 710640 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_81 CoreSite 2880 309960 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_82 CoreSite 2880 313740 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_83 CoreSite 2880 317520 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_84 CoreSite 2880 321300 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_85 CoreSite 2880 325080 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_86 CoreSite 2880 328860 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_87 CoreSite 2880 332640 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_88 CoreSite 2880 336420 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_89 CoreSite 2880 340200 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_90 CoreSite 2880 343980 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_91 CoreSite 2880 347760 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_92 CoreSite 2880 351540 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_93 CoreSite 2880 355320 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_94 CoreSite 2880 359100 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_95 CoreSite 2880 362880 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_96 CoreSite 2880 366660 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_97 CoreSite 2880 370440 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_98 CoreSite 2880 374220 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_99 CoreSite 2880 378000 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_100 CoreSite 2880 381780 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_101 CoreSite 2880 385560 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_102 CoreSite 2880 389340 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_103 CoreSite 2880 393120 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_104 CoreSite 2880 396900 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_105 CoreSite 2880 400680 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_106 CoreSite 2880 404460 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_107 CoreSite 2880 408240 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_108 CoreSite 2880 412020 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_109 CoreSite 2880 415800 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_110 CoreSite 2880 419580 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_111 CoreSite 2880 423360 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_112 CoreSite 2880 427140 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_113 CoreSite 2880 430920 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_114 CoreSite 2880 434700 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_115 CoreSite 2880 438480 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_116 CoreSite 2880 442260 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_117 CoreSite 2880 446040 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_118 CoreSite 2880 449820 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_119 CoreSite 2880 453600 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_120 CoreSite 2880 457380 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_121 CoreSite 2880 461160 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_122 CoreSite 2880 464940 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_123 CoreSite 2880 468720 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_124 CoreSite 2880 472500 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_125 CoreSite 2880 476280 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_126 CoreSite 2880 480060 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_127 CoreSite 2880 483840 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_128 CoreSite 2880 487620 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_129 CoreSite 2880 491400 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_130 CoreSite 2880 495180 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_131 CoreSite 2880 498960 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_132 CoreSite 2880 502740 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_133 CoreSite 2880 506520 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_134 CoreSite 2880 510300 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_135 CoreSite 2880 514080 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_136 CoreSite 2880 517860 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_137 CoreSite 2880 521640 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_138 CoreSite 2880 525420 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_139 CoreSite 2880 529200 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_140 CoreSite 2880 532980 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_141 CoreSite 2880 536760 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_142 CoreSite 2880 540540 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_143 CoreSite 2880 544320 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_144 CoreSite 2880 548100 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_145 CoreSite 2880 551880 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_146 CoreSite 2880 555660 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_147 CoreSite 2880 559440 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_148 CoreSite 2880 563220 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_149 CoreSite 2880 567000 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_150 CoreSite 2880 570780 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_151 CoreSite 2880 574560 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_152 CoreSite 2880 578340 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_153 CoreSite 2880 582120 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_154 CoreSite 2880 585900 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_155 CoreSite 2880 589680 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_156 CoreSite 2880 593460 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_157 CoreSite 2880 597240 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_158 CoreSite 2880 601020 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_159 CoreSite 2880 604800 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_160 CoreSite 2880 608580 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_161 CoreSite 2880 612360 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_162 CoreSite 2880 616140 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_163 CoreSite 2880 619920 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_164 CoreSite 2880 623700 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_165 CoreSite 2880 627480 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_166 CoreSite 2880 631260 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_167 CoreSite 2880 635040 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_168 CoreSite 2880 638820 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_169 CoreSite 2880 642600 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_170 CoreSite 2880 646380 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_171 CoreSite 2880 650160 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_172 CoreSite 2880 653940 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_173 CoreSite 2880 657720 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_174 CoreSite 2880 661500 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_175 CoreSite 2880 665280 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_176 CoreSite 2880 669060 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_177 CoreSite 2880 672840 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_178 CoreSite 2880 676620 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_179 CoreSite 2880 680400 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_180 CoreSite 2880 684180 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_181 CoreSite 2880 687960 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_182 CoreSite 2880 691740 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_183 CoreSite 2880 695520 FS DO 2221 BY 1 STEP 480 0 ; +ROW ROW_184 CoreSite 2880 699300 N DO 2221 BY 1 STEP 480 0 ; +ROW ROW_185 CoreSite 2880 703080 FS DO 2221 BY 1 STEP 480 0 ; +TRACKS X 480 DO 2232 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 2232 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 2232 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 2232 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 470 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 710140 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 710140 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 710140 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 710140 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 710140 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 710140 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 710140 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 710140 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 710140 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 710140 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 710140 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 710140 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 710140 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 710140 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 710140 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 710140 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 710140 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 710140 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 710140 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 710140 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 710140 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 710140 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 710140 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 710140 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 710140 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 710140 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 710140 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 710140 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 710140 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 710140 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 710140 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 710140 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 710140 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 710140 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 710140 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 710140 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 710140 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 710140 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 710140 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 710140 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 710140 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 710140 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 710140 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_6x2_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_6x2_pgvdd.def new file mode 100644 index 0000000..4bcbe78 --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_6x2_pgvdd.def @@ -0,0 +1,323 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1289280 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 2674 BY 1 STEP 480 0 ; +TRACKS X 480 DO 2685 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 2685 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 2685 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 565 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_6x4_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_6x4_pgvdd.def new file mode 100644 index 0000000..26dde1e --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_6x4_pgvdd.def @@ -0,0 +1,428 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1289280 710640 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_81 CoreSite 2880 309960 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_82 CoreSite 2880 313740 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_83 CoreSite 2880 317520 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_84 CoreSite 2880 321300 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_85 CoreSite 2880 325080 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_86 CoreSite 2880 328860 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_87 CoreSite 2880 332640 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_88 CoreSite 2880 336420 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_89 CoreSite 2880 340200 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_90 CoreSite 2880 343980 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_91 CoreSite 2880 347760 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_92 CoreSite 2880 351540 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_93 CoreSite 2880 355320 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_94 CoreSite 2880 359100 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_95 CoreSite 2880 362880 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_96 CoreSite 2880 366660 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_97 CoreSite 2880 370440 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_98 CoreSite 2880 374220 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_99 CoreSite 2880 378000 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_100 CoreSite 2880 381780 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_101 CoreSite 2880 385560 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_102 CoreSite 2880 389340 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_103 CoreSite 2880 393120 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_104 CoreSite 2880 396900 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_105 CoreSite 2880 400680 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_106 CoreSite 2880 404460 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_107 CoreSite 2880 408240 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_108 CoreSite 2880 412020 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_109 CoreSite 2880 415800 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_110 CoreSite 2880 419580 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_111 CoreSite 2880 423360 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_112 CoreSite 2880 427140 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_113 CoreSite 2880 430920 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_114 CoreSite 2880 434700 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_115 CoreSite 2880 438480 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_116 CoreSite 2880 442260 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_117 CoreSite 2880 446040 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_118 CoreSite 2880 449820 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_119 CoreSite 2880 453600 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_120 CoreSite 2880 457380 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_121 CoreSite 2880 461160 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_122 CoreSite 2880 464940 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_123 CoreSite 2880 468720 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_124 CoreSite 2880 472500 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_125 CoreSite 2880 476280 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_126 CoreSite 2880 480060 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_127 CoreSite 2880 483840 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_128 CoreSite 2880 487620 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_129 CoreSite 2880 491400 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_130 CoreSite 2880 495180 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_131 CoreSite 2880 498960 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_132 CoreSite 2880 502740 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_133 CoreSite 2880 506520 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_134 CoreSite 2880 510300 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_135 CoreSite 2880 514080 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_136 CoreSite 2880 517860 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_137 CoreSite 2880 521640 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_138 CoreSite 2880 525420 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_139 CoreSite 2880 529200 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_140 CoreSite 2880 532980 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_141 CoreSite 2880 536760 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_142 CoreSite 2880 540540 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_143 CoreSite 2880 544320 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_144 CoreSite 2880 548100 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_145 CoreSite 2880 551880 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_146 CoreSite 2880 555660 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_147 CoreSite 2880 559440 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_148 CoreSite 2880 563220 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_149 CoreSite 2880 567000 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_150 CoreSite 2880 570780 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_151 CoreSite 2880 574560 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_152 CoreSite 2880 578340 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_153 CoreSite 2880 582120 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_154 CoreSite 2880 585900 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_155 CoreSite 2880 589680 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_156 CoreSite 2880 593460 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_157 CoreSite 2880 597240 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_158 CoreSite 2880 601020 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_159 CoreSite 2880 604800 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_160 CoreSite 2880 608580 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_161 CoreSite 2880 612360 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_162 CoreSite 2880 616140 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_163 CoreSite 2880 619920 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_164 CoreSite 2880 623700 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_165 CoreSite 2880 627480 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_166 CoreSite 2880 631260 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_167 CoreSite 2880 635040 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_168 CoreSite 2880 638820 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_169 CoreSite 2880 642600 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_170 CoreSite 2880 646380 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_171 CoreSite 2880 650160 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_172 CoreSite 2880 653940 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_173 CoreSite 2880 657720 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_174 CoreSite 2880 661500 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_175 CoreSite 2880 665280 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_176 CoreSite 2880 669060 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_177 CoreSite 2880 672840 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_178 CoreSite 2880 676620 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_179 CoreSite 2880 680400 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_180 CoreSite 2880 684180 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_181 CoreSite 2880 687960 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_182 CoreSite 2880 691740 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_183 CoreSite 2880 695520 FS DO 2674 BY 1 STEP 480 0 ; +ROW ROW_184 CoreSite 2880 699300 N DO 2674 BY 1 STEP 480 0 ; +ROW ROW_185 CoreSite 2880 703080 FS DO 2674 BY 1 STEP 480 0 ; +TRACKS X 480 DO 2685 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 2685 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 2685 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 565 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 710140 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 710140 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 710140 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 710140 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 710140 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 710140 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 710140 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 710140 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 710140 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 710140 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 710140 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 710140 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 710140 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 710140 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 710140 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 710140 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 710140 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 710140 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 710140 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 710140 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 710140 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 710140 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 710140 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 710140 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 710140 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 710140 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 710140 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 710140 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 710140 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 710140 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 710140 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 710140 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 710140 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 710140 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 710140 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 710140 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 710140 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 710140 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 710140 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 710140 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 710140 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 710140 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 710140 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_8x2_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_8x2_pgvdd.def new file mode 100644 index 0000000..1b8ccee --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_8x2_pgvdd.def @@ -0,0 +1,323 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1724160 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 3580 BY 1 STEP 480 0 ; +TRACKS X 480 DO 3591 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 3591 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 3591 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 3591 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 756 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/def/tt_block_8x4_pgvdd.def b/tech/ihp-sg13cmos5l/def/tt_block_8x4_pgvdd.def new file mode 100644 index 0000000..a493183 --- /dev/null +++ b/tech/ihp-sg13cmos5l/def/tt_block_8x4_pgvdd.def @@ -0,0 +1,428 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1724160 710640 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_81 CoreSite 2880 309960 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_82 CoreSite 2880 313740 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_83 CoreSite 2880 317520 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_84 CoreSite 2880 321300 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_85 CoreSite 2880 325080 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_86 CoreSite 2880 328860 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_87 CoreSite 2880 332640 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_88 CoreSite 2880 336420 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_89 CoreSite 2880 340200 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_90 CoreSite 2880 343980 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_91 CoreSite 2880 347760 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_92 CoreSite 2880 351540 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_93 CoreSite 2880 355320 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_94 CoreSite 2880 359100 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_95 CoreSite 2880 362880 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_96 CoreSite 2880 366660 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_97 CoreSite 2880 370440 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_98 CoreSite 2880 374220 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_99 CoreSite 2880 378000 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_100 CoreSite 2880 381780 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_101 CoreSite 2880 385560 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_102 CoreSite 2880 389340 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_103 CoreSite 2880 393120 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_104 CoreSite 2880 396900 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_105 CoreSite 2880 400680 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_106 CoreSite 2880 404460 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_107 CoreSite 2880 408240 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_108 CoreSite 2880 412020 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_109 CoreSite 2880 415800 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_110 CoreSite 2880 419580 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_111 CoreSite 2880 423360 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_112 CoreSite 2880 427140 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_113 CoreSite 2880 430920 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_114 CoreSite 2880 434700 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_115 CoreSite 2880 438480 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_116 CoreSite 2880 442260 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_117 CoreSite 2880 446040 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_118 CoreSite 2880 449820 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_119 CoreSite 2880 453600 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_120 CoreSite 2880 457380 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_121 CoreSite 2880 461160 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_122 CoreSite 2880 464940 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_123 CoreSite 2880 468720 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_124 CoreSite 2880 472500 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_125 CoreSite 2880 476280 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_126 CoreSite 2880 480060 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_127 CoreSite 2880 483840 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_128 CoreSite 2880 487620 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_129 CoreSite 2880 491400 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_130 CoreSite 2880 495180 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_131 CoreSite 2880 498960 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_132 CoreSite 2880 502740 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_133 CoreSite 2880 506520 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_134 CoreSite 2880 510300 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_135 CoreSite 2880 514080 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_136 CoreSite 2880 517860 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_137 CoreSite 2880 521640 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_138 CoreSite 2880 525420 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_139 CoreSite 2880 529200 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_140 CoreSite 2880 532980 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_141 CoreSite 2880 536760 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_142 CoreSite 2880 540540 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_143 CoreSite 2880 544320 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_144 CoreSite 2880 548100 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_145 CoreSite 2880 551880 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_146 CoreSite 2880 555660 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_147 CoreSite 2880 559440 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_148 CoreSite 2880 563220 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_149 CoreSite 2880 567000 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_150 CoreSite 2880 570780 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_151 CoreSite 2880 574560 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_152 CoreSite 2880 578340 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_153 CoreSite 2880 582120 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_154 CoreSite 2880 585900 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_155 CoreSite 2880 589680 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_156 CoreSite 2880 593460 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_157 CoreSite 2880 597240 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_158 CoreSite 2880 601020 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_159 CoreSite 2880 604800 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_160 CoreSite 2880 608580 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_161 CoreSite 2880 612360 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_162 CoreSite 2880 616140 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_163 CoreSite 2880 619920 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_164 CoreSite 2880 623700 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_165 CoreSite 2880 627480 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_166 CoreSite 2880 631260 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_167 CoreSite 2880 635040 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_168 CoreSite 2880 638820 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_169 CoreSite 2880 642600 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_170 CoreSite 2880 646380 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_171 CoreSite 2880 650160 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_172 CoreSite 2880 653940 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_173 CoreSite 2880 657720 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_174 CoreSite 2880 661500 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_175 CoreSite 2880 665280 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_176 CoreSite 2880 669060 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_177 CoreSite 2880 672840 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_178 CoreSite 2880 676620 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_179 CoreSite 2880 680400 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_180 CoreSite 2880 684180 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_181 CoreSite 2880 687960 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_182 CoreSite 2880 691740 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_183 CoreSite 2880 695520 FS DO 3580 BY 1 STEP 480 0 ; +ROW ROW_184 CoreSite 2880 699300 N DO 3580 BY 1 STEP 480 0 ; +ROW ROW_185 CoreSite 2880 703080 FS DO 3580 BY 1 STEP 480 0 ; +TRACKS X 480 DO 3591 STEP 480 LAYER Metal1 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ; +TRACKS X 480 DO 3591 STEP 480 LAYER Metal2 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 3591 STEP 480 LAYER Metal3 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ; +TRACKS X 480 DO 3591 STEP 480 LAYER Metal4 ; +TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ; +TRACKS X 1640 DO 756 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 710140 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 710140 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 710140 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 710140 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 710140 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 710140 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 710140 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 710140 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 710140 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 710140 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 710140 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 710140 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 710140 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 710140 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 710140 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 710140 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 710140 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 710140 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 710140 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 710140 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 710140 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 710140 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 710140 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 710140 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 37440 710140 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 33600 710140 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 29760 710140 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 710140 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 710140 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 710140 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 710140 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 710140 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 710140 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 710140 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 710140 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 710140 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 710140 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 710140 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 710140 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 710140 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 710140 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 710140 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 710140 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/ihp-sg13cmos5l/tile_sizes.yaml b/tech/ihp-sg13cmos5l/tile_sizes.yaml new file mode 100644 index 0000000..cb96d4e --- /dev/null +++ b/tech/ihp-sg13cmos5l/tile_sizes.yaml @@ -0,0 +1,17 @@ +1x1: "0 0 202.08 154.98" +1x2: "0 0 202.08 313.74" +2x1: "0 0 419.52 154.98" +2x2: "0 0 419.52 313.74" +3x1: "0 0 636.96 154.98" +3x2: "0 0 636.96 313.74" +3x4: "0 0 636.96 710.64" +4x1: "0 0 854.40 154.98" +4x2: "0 0 854.40 313.74" +4x4: "0 0 854.40 710.64" +5x4: "0 0 1071.84 710.64" +6x1: "0 0 1289.28 154.98" +6x2: "0 0 1289.28 313.74" +6x4: "0 0 1289.28 710.64" +8x1: "0 0 1724.16 154.98" +8x2: "0 0 1724.16 313.74" +8x4: "0 0 1724.16 710.64" diff --git a/tech/ihp-sg13cmos5l/tt_logo_corner.gds b/tech/ihp-sg13cmos5l/tt_logo_corner.gds new file mode 100644 index 0000000000000000000000000000000000000000..8584ca62eb7fa7796b53174a838d2be90c1897ff GIT binary patch literal 16638 zcmaKzU+CXe8OP6e|A(%$CMix-GFvii$gm|tmJAuTYNev4vWbo<&Xzi9mX0AKe#MAg zNDPV?A?U?G1HlOfyNK9@(Jn;1knmy`BSdyFLeQ}H>pACrzULP_pC8PZJkNPQpMU2( z=kK?yC`*>yU)If*to(ObT9%aMWmeXW|6jhcWW|94yY}thyMNcC`=9yQo@dJ1rOR*s z-fzD1{lC9@;k(;Tefz{8etJ(?w|pYPivN$WY*i^M)+{N1Ei1mXq%12NE?Zj0zuB)( zl=0u_TXuOV)*lLesruK?l-ZG!r9kP+`yb3{yO`?#ysnhl#ZutX^QD|SGND{S(foo2d*-Cv2({?e{Kd1%7p*>P^K7yO`>q+!wk6uXv&AO~nbjnChQ67`g(#_VcPY6({Us zs^4=gbOm1ZSk;?~6LvAxKk{1W3cULMsy7uU>|&~a_;lzByk5G1JeU(0hOT zXbJvfZEd@z?P8{n?|Wi>{m$>5E3-Scm15d1ruw44w~q7QQvSIro}trrG1XJYzi4fT zx_^FOZ3Ck1Fx9JW_cpU;q3X?{Ev0(e3gzMD`rcgMv|UW~v=z$3EA+k4o3@Lop0+}H zc-7XbH*FVFJ#B^Z@EUzbu5a2drh3{6<>B?0RlRAunCfXOl!rHbTJ@&wVydUDP#&)T zsOnAI#Z*sQp*+0ly{b2D7gPPUTdNM<{7%)I#A*IifBmMagB#zddXqTKpX$H9zUttn z<5h1Gr}4Q8hfi*gchO01X#P~MyhVBP)acHExaaknyg@ubsqe{#5_^8GStcLB_ipKX=+LX8PG9M@qS{r3A-k=iY4> zQ~h0QOSCztJlWeWZJD;%{HcD|vHH&8XR1TIbCdgN{#3vHx_VuB%!%yY7R5GpXN{Xw?9;`2XA?$%pN^BC->9*sea4jwLDb68+wy? z&7bNYc(dL&)OfS!UUD(d(fq0YwgdIL@YbV|2RgZr=1=vT4_6)JpW16D@tQx?4`t$7 z=((ojG=Hie?lImK^_X`Chi6Om!#j>|#rNi$!QtDa`r#W#UE_UI=ipE`QvFazqpjR` zy0#fO)a_J1w6Vwm_r6aSf_%flahzW5*Unm^Su-a`k+YooPYO!b-@ zg$|C-&bfU+l4Ln!Bju=F_ANzJ0Llr`7?ctRp=u>yI6CUa~HH-O!dPU zhcQ^sz2v<%_JOH>7^5xfJIIT}*e=yGUssnruu*B9Z6RpV-NTJ&~`D^ zYt057Yc`9bVB%Rq%b)_i+u{b}`itbu{Wa*Qd_= zKAJz(`?`>Kc;w`q+)wkT`k{?QTOH?sL)%RC!#7$q_wao*f2tpHMC6)r4m;$QR8RbK zs`rq($ehQtT}<^uj*DE$+?$*UhuoOzhdR#Mf1kVgKAJz(4>>ye0M-!b3*eC3Q~l6K zunyMO9vr9nC-vwkM_Z5Pw)?^xCQ$VF=}zK`b5^kw6F zbGY`)K}Df6JNr+)!hdvg^$`c@NE>>iJ$=4^oGJ|JaZEG zGg1DH=QnvD&7bP;y-=?Q$zgxmG$;4d{HcDE`bnM}YRnhwpr-9&s=x1Cy&l}VyOdWy zos;`%{#5_1WwpLTjd|idnzV!FPxTMJTdxOM?|tj|oZL_Ir}|spsLu_RD`LIY|n)A3T8KhMa746OBJv4u+-}X?wF4R~t*5OU=qxn<4*8SNpjeXQFKCJ7&rtM;?zjJ53E~LMF zvCPSRG=Hk6-EsB;D)&VDGi?_q^^`~d`k9)4P20s(U-UjrTKex!;xvD%*Z3mJL**dGADzT&{#37V zQ*#M|r5RPMjk#iP!w8UhOkZ{0~oy2SYRIj`r<)QkTIB#MSulZ9wW&Mw`+Q$qH zv|UW~!!_bwwU634+*_(2o-y8)_HjFhca!RecO2hJ9m- zDNh{gn&uy!wu`BLsH0KWmH#`3x}EBWHWF=3uSC;huk))r#x}UmDWPr#Z*7!*tlokI~;OzsvmMZW4He9c=n-h znAD>q&iL(k_qL0vp7AO=IMyA$z3pPEXTF9Gj&+y1XS+D5M~7Zx^=Lz;?P99extGwv zhfi0%Nu1_S^*VRsGiJ>FdfTV%5~ukm_2?)!<{ol~?P97Q&d9}CJ93tDAn}?%)$80+ zl!s&PC3h01`BOb-1kpjxAd<69+r?BroKalV_mJ0#)BKZq`Yg)rzo+(PrtM;?AI?}V z>O1Kdh|~O&diq?-F_v}T4Q&@w{cuKf(b$1}PQ2z%^_2P5rM2vd^>r+1+AgO0H7Dzs z1&(7M`URb-@!8l(Jv#JX}g%}hcmj1#%}a0#A*IXJ!3w~afX=w#I#*Z^}`wC zMPpCLY5qw)V^+#7=pN{gOxwj&zfxMt!*T5FIL$w)M@PBesSeT)nYN3Qddj0ewovB+ zrtM;?AI^v`ntRZ%5vTc6J@fl^MxC{%=!Z<(#Z*sx<~)${^kb&&VyYi<{Gz!RbFiUr zNcBS>wP^0h-0#}0y$?(ELm#>5*?9*;-Q1>2ZNKMF>qi@d{mQLHnNj*CBsPn6`_Pddj0$o9E0&r|sgT9vyn+tiG1V+MVs}7>&x^ei({^!EPkHp}b7K#}v|XIkQy#tg{JxgG{kj^j#huinqnySp zu?BA1E>7w>`;A^>z2vPqogPxX9f%0tcbV-47}T}<^l ze-%2YIalaS;xvD%*ExyMLCyJM4cH`3^QU^9(+C~ZoHN#NP2x0vswdx59%{}Td#I-E zVyb72o$^p~?$`r0Z5LBLYxR_en&-#frD?mE>Ng**I;i=6=uP4@f2yaypgh!kzwafo zcWAqq>ggxYLCy1H9AMfmruuQuNMo7Mo5X4URKIoSe9uK=sn~-wiPQY4-g^~L^ZeLD zG>Oyvsos0_P-DT+o5X4UNj>E$r}=*DA)2;}sos0#aMzplw?Ve-v-=gr_6XG?0s`p+e)I6W_8=b^!{!~w%Mh7+DpFMrUoVHJ_ zAN0LO_WCr>54}mewkMfhf86udxVit9f%7wrXPZCMNB^jDLCw2om%LnxX}g%|7wuVU zouL1g=GiOj^R&IpRPVh;sI`FpTN-{lL%ils_1-Iln(z1D((v0E;x&J&_g)`-vDDwv zn8a)TR6p+7X};foi*xW|jo18>dUTZ2JU@PmW7;mJ`ti)o_*))+yF;AjpVXtHoaXuQ zTOQMPG1ZS}ZWd0>e+$HKe~8oklX`TN(>yXfts)P-xBfr58^a`s;8ep z2Q|-*^H-+rVyb`i;QY)B^UdKmM-i|2Q$6jIb_+G