diff --git a/configure.py b/configure.py
index 6d00e24..3b811a0 100755
--- a/configure.py
+++ b/configure.py
@@ -27,7 +27,7 @@ class Projects():
         self.projects = []
         project_list = [entry for entry in os.listdir(self.project_dir) if os.path.isdir(os.path.join(self.project_dir, entry))]
         if args.test:
-            project_list = ['tt_um_factory_test']
+            project_list = ['tt_um_chip_rom', 'tt_um_factory_test']
         elif args.sta_projects:
             project_list = ['tt_um_loopback']
 
@@ -242,8 +242,6 @@ if __name__ == '__main__':
 
     if args.update_shuttle:
         shuttle.configure_mux()
-        if args.test:
-            shuttle.write_gl_config()
         rom.write_rom()
         if not args.test:
             docs.build_index()
diff --git a/rom/tt_um_chip_rom.v b/rom/tt_um_chip_rom.v
index c1b9486..9570b56 100644
--- a/rom/tt_um_chip_rom.v
+++ b/rom/tt_um_chip_rom.v
@@ -8,6 +8,10 @@
 
 `default_nettype none
 
+`ifndef ROM_VMEM_PATH
+    `define ROM_VMEM_PATH "rom.vmem"
+`endif
+
 module tt_um_chip_rom (
 	input  wire [7:0] ui_in,	// Dedicated inputs
 	output wire [7:0] uo_out,	// Dedicated outputs
@@ -22,7 +26,7 @@ module tt_um_chip_rom (
 	reg [7:0] rom_data [0:255];
 
   initial begin
-		$readmemh("rom.vmem", rom_data);
+		$readmemh(`ROM_VMEM_PATH, rom_data);
 	end
 	
 	assign uo_out  = rom_data[ui_in];
diff --git a/shuttle.py b/shuttle.py
index 9cb4524..0cdf8a6 100644
--- a/shuttle.py
+++ b/shuttle.py
@@ -25,14 +25,6 @@ class ShuttleConfig():
         self.script_dir = os.path.dirname(os.path.realpath(__file__))
         self.modules_yaml_name = modules_yaml_name
 
-    def write_gl_config(self):
-        with open('verilog/includes/includes.gl.caravel_user_project', 'w') as fh:
-            fh.write('-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_ctrl.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_mux.v\n')
-            for project in self.projects:
-                fh.write(f'-v $(USER_PROJECT_VERILOG)/../projects/{project.top_module}/{project.get_gl_verilog_filename()}\n')
-
     def configure_mux(self):
         with open(self.modules_yaml_name, 'r') as modules_file:
             module_config = yaml.safe_load(modules_file)
@@ -127,7 +119,7 @@ class ShuttleConfig():
 
 
     def copy_final_results(self):
-        macros = ["tt_ctrl", "tt_mux", "tt_top"]
+        macros = ["tt_um_chip_rom", "tt_ctrl", "tt_mux", "tt_top"]
 
         logging.info('copying final results:')
         for macro in macros: