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fix: remove openlane1 config generator

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it's no longer needed for OpenLane2
This commit is contained in:
Uri Shaked
2023-06-17 23:07:39 +03:00
parent 8549004599
commit 25488cf0df
3 changed files with 0 additions and 144 deletions
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caravel_template/upw_config.json
-124
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@@ -1,124 +0,0 @@
{
"DESIGN_NAME": "user_project_wrapper",
"VERILOG_FILES": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/rtl/user_project_wrapper.v",
"dir::../../tt-multiplexer/proto/tt_top.v",
"dir::../../tt-multiplexer/proto/tt_user_module.v"
],
"VERILOG_FILES_BLACKBOX": [
"dir::../../tt-multiplexer/proto/tt_mux.v",
"dir::../../tt-multiplexer/proto/tt_ctrl.v",
"dir::../../verilog/blackbox_project_includes.v"
],
"ROUTING_CORES": 8,
"CLOCK_PERIOD": 25,
"CLOCK_PORT": "wb_clk_i",
"CLOCK_NET": "mprj.clk",
"FP_PDN_MACRO_HOOKS": [
"tt_top1\\.ctrl_I vccd1 vssd1 vccd1 vssd1,",
"tt_top1\\..*mux_I vccd1 vssd1 vccd1 vssd1,",
"tt_top1\\..*sram vccd1 vssd1 vccd1 vssd1,",
"tt_top1\\..*tt_um_I vccd1 vssd1 vccd1 vssd1"
],
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
"PDN_CFG": "dir::pdn_cfg.tcl",
"MAGIC_DEF_LABELS": 0,
"EXTRA_LEFS": [
"dir::../../lef/tt_ctrl.lef",
"dir::../../lef/tt_mux.lef"
],
"EXTRA_GDS_FILES": [
"dir::../../gds/tt_ctrl.gds",
"dir::../../gds/tt_mux.gds"
],
"RUN_KLAYOUT_XOR": 0,
"RUN_KLAYOUT_DRC": 0,
"RUN_MAGIC_DRC": 0,
"IO_SYNC": 0,
"FP_PDN_CHECK_NODES": 0,
"GRT_ALLOW_CONGESTION": 1,
"GRT_LAYER_ADJUSTMENTS": "1,0.99,0.99,0,0,0",
"SYNTH_ELABORATE_ONLY": 1,
"PL_RANDOM_GLB_PLACEMENT": 1,
"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
"SYNTH_FLAT_TOP": 1,
"FP_PDN_ENABLE_RAILS": 0,
"DIODE_INSERTION_STRATEGY": 0,
"RUN_FILL_INSERTION": 0,
"RUN_TAP_DECAP_INSERTION": 0,
"FP_PDN_VPITCH": 140,
"FP_PDN_VOFFSET": 186,
"FP_PDN_HPITCH": 50,
"FP_PDN_HOFFSET": 160,
"CLOCK_TREE_SYNTH": 0,
"QUIT_ON_LVS_ERROR": "0",
"MAGIC_ZEROIZE_ORIGIN": 0,
"FP_SIZING": "absolute",
"RUN_CVC": 0,
"UNIT": 2.4,
"FP_IO_VEXTEND": "expr::2 * $UNIT",
"FP_IO_HEXTEND": "expr::2 * $UNIT",
"FP_IO_VLENGTH": "expr::$UNIT",
"FP_IO_HLENGTH": "expr::$UNIT",
"FP_IO_VTHICKNESS_MULT": 4,
"FP_IO_HTHICKNESS_MULT": 4,
"FP_PDN_CORE_RING": 1,
"FP_PDN_CORE_RING_VWIDTH": 3.1,
"FP_PDN_CORE_RING_HWIDTH": 3.1,
"FP_PDN_CORE_RING_VOFFSET": 12.45,
"FP_PDN_CORE_RING_HOFFSET": 12.45,
"FP_PDN_CORE_RING_VSPACING": 1.7,
"FP_PDN_CORE_RING_HSPACING": 1.7,
"FP_PDN_VWIDTH": 3.1,
"FP_PDN_HWIDTH": 3.1,
"FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
"FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
"VDD_NETS": [
"vccd1",
"vccd2",
"vdda1",
"vdda2"
],
"GND_NETS": [
"vssd1",
"vssd2",
"vssa1",
"vssa2"
],
"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
"pdk::sky130*": {
"RT_MAX_LAYER": "met4",
"DIE_AREA": "0 0 2920 3520",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
"scl::sky130_fd_sc_hd": {
"CLOCK_PERIOD": 25
},
"scl::sky130_fd_sc_hdll": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
"CLOCK_PERIOD": 10,
"SYNTH_MAX_FANOUT": 5
},
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
},
"pdk::gf180mcuC": {
"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
"FP_PDN_CHECK_NODES": 0,
"FP_PDN_ENABLE_RAILS": 0,
"RT_MAX_LAYER": "Metal4",
"DIE_AREA": "0 0 3000 3000",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
"PL_OPENPHYSYN_OPTIMIZATIONS": 0,
"DIODE_INSERTION_STRATEGY": 0,
"MAGIC_WRITE_FULL_LEF": 0
}
}