From 282de3777aac1cc9d18259b120e972ff5bd19829 Mon Sep 17 00:00:00 2001 From: Matt Venn Date: Tue, 21 Feb 2023 18:19:52 +0100 Subject: [PATCH] first pass after splitting configure.py and incorporating sssummarizer --- categories.json | 184 ++++++++++++++++++++++++++++++++++++++++ defs.json | 1 + docs/project_header.md | 11 +++ docs/project_preview.md | 30 +++++++ documentation.py | 59 +++++++++++++ lint.sh | 1 + project.py | 97 +++++++++++++++++++++ reports.py | 116 +++++++++++++++++++++++++ tt_tool.py | 71 ++++++++++++++++ 9 files changed, 570 insertions(+) create mode 100644 categories.json create mode 100644 defs.json create mode 100644 docs/project_header.md create mode 100644 docs/project_preview.md create mode 100644 documentation.py create mode 100755 lint.sh create mode 100644 project.py create mode 100755 reports.py create mode 100755 tt_tool.py diff --git a/categories.json b/categories.json new file mode 100644 index 0000000..85f0b9b --- /dev/null +++ b/categories.json @@ -0,0 +1,184 @@ +{ + "categories" : [ + "AND", + "OR", + "NAND", + "NOR", + "Clock", + "Flip Flops", + "Multiplexer", + "Latch", + "Inverter", + "Buffer", + "Fill", + "Tap", + "Diode", + "Combo Logic", + "Misc" + ], + "map" : { + "a2111o" : 13, + "a2111oi" : 13, + "a211o" : 13, + "a211oi" : 13, + "a21bo" : 13, + "a21boi" : 0, + "a21o" : 13, + "a21oi" : 13, + "a221o" : 13, + "a221oi" : 13, + "a222oi" : 13, + "a22o" : 13, + "a22oi" : 13, + "a2bb2o" : 13, + "a2bb2oi" : 13, + "a311o" : 13, + "a311oi" : 13, + "a31o" : 13, + "a31oi" : 13, + "a32o" : 13, + "a32oi" : 13, + "a41o" : 13, + "a41oi" : 13, + "and2" : 0, + "and2b" : 13, + "and3" : 0, + "and3b" : 13, + "and4" : 0, + "and4b" : 13, + "and4bb" : 13, + "buf" : 9, + "bufbuf" : 9, + "bufinv" : 9, + "clkbuf" : 9, + "clkdlybuf4s15" : 4, + "clkdlybuf4s18" : 4, + "clkdlybuf4s25" : 4, + "clkdlybuf4s50" : 4, + "clkinv" : 4, + "clkinvlp" : 4, + "conb" : 14, + "decap" : 10, + "dfbbn" : 5, + "dfbbp" : 5, + "dfrbp" : 5, + "dfrtn" : 5, + "dfrtp" : 5, + "dfsbp" : 5, + "dfstp" : 5, + "dfxbp" : 5, + "dfxtp" : 5, + "diode" : 12, + "dlclkp" : 4, + "dlrbn" : 7, + "dlrbp" : 7, + "dlrtn" : 7, + "dlrtp" : 7, + "dlxbn" : 7, + "dlxbp" : 7, + "dlxtn" : 7, + "dlxtp" : 7, + "dlygate4sd1" : 14, + "dlygate4sd2" : 14, + "dlygate4sd3" : 14, + "dlymetal6s2s" : 14, + "dlymetal6s4s" : 14, + "dlymetal6s6s" : 14, + "ebufn" : 14, + "edfxbp" : 5, + "edfxtp" : 5, + "einvn" : 14, + "einvp" : 11, + "fa" : 14, + "fah" : 14, + "fahcin" : 14, + "fahcon" : 14, + "fill" : 10, + "ha" : 14, + "inv" : 8, + "lpflow_bleeder" : 14, + "lpflow_clkbufkapwr" : 4, + "lpflow_clkinvkapwr" : 4, + "lpflow_decapkapwr" : 10, + "lpflow_inputiso0n" : 14, + "lpflow_inputiso0p" : 14, + "lpflow_inputiso1n" : 14, + "lpflow_inputiso1p" : 14, + "lpflow_inputisolatch" : 14, + "lpflow_isobufsrc" : 14, + "lpflow_isobufsrckapwr" : 14, + "lpflow_lsbuf_lh_hl_isowell_tap" : 9, + "lpflow_lsbuf_lh_isowell" : 9, + "lpflow_lsbuf_lh_isowell_tap" : 9, + "macro_sparecell" : 14, + "maj3" : 14, + "mux2" : 6, + "mux2i" : 6, + "mux4" : 6, + "nand2" : 2, + "nand2b" : 2, + "nand3" : 2, + "nand3b" : 13, + "nand4" : 2, + "nand4b" : 13, + "nand4bb" : 13, + "nor2" : 3, + "nor2b" : 13, + "nor3" : 3, + "nor3b" : 13, + "nor4" : 3, + "nor4b" : 13, + "nor4bb" : 13, + "o2111a" : 13, + "o2111ai" : 13, + "o211a" : 13, + "o211ai" : 13, + "o21a" : 13, + "o21ai" : 13, + "o21ba" : 13, + "o21bai" : 13, + "o221a" : 13, + "o221ai" : 13, + "o22a" : 13, + "o22ai" : 13, + "o2bb2a" : 13, + "o2bb2ai" : 13, + "o311a" : 13, + "o311ai" : 13, + "o31a" : 13, + "o31ai" : 13, + "o32a" : 13, + "o32ai" : 13, + "o41a" : 13, + "o41ai" : 13, + "or2" : 1, + "or2b" : 13, + "or3" : 1, + "or3b" : 13, + "or4" : 1, + "or4b" : 13, + "or4bb" : 13, + "probe_p" : 14, + "probec_p" : 14, + "sdfbbn" : 5, + "sdfbbp" : 5, + "sdfrbp" : 5, + "sdfrtn" : 5, + "sdfrtp" : 5, + "sdfsbp" : 5, + "sdfstp" : 5, + "sdfxbp" : 5, + "sdfxtp" : 5, + "sdlclkp" : 4, + "sedfxbp" : 5, + "sedfxtp" : 5, + "tap" : 11, + "tapvgnd" : 11, + "tapvgnd2" : 11, + "tapvpwrvgnd" : 11, + "xnor2" : 3, + "xnor3" : 3, + "xor2" : 1, + "xor3" : 1 + } +} diff --git a/defs.json b/defs.json new file mode 100644 index 0000000..527cc2d --- /dev/null +++ b/defs.json @@ -0,0 +1 @@ +{"nand3": {"description": "3-input NAND.", "file_prefix": "sky130_fd_sc_hd__nand3", "library": "sky130_fd_sc_hd", "name": "nand3", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand3"}, "o31ai": {"description": "3-input OR into 2-input NAND.", "equation": "Y = !((A1 | A2 | A3) & B1)", "file_prefix": "sky130_fd_sc_hd__o31ai", "library": "sky130_fd_sc_hd", "name": "o31ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o31ai"}, "or4bb": {"description": "4-input OR, first two inputs inverted.", "file_prefix": "sky130_fd_sc_hd__or4bb", "library": "sky130_fd_sc_hd", "name": "or4bb", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C_N", "input", ""], ["signal", "D_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or4bb"}, "tap": {"description": "Tap cell with no tap connections (no contacts on metal1).", "file_prefix": "sky130_fd_sc_hd__tap", "library": "sky130_fd_sc_hd", "name": "tap", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__tap"}, "or4": {"description": "4-input OR.", "file_prefix": "sky130_fd_sc_hd__or4", "library": "sky130_fd_sc_hd", "name": "or4", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or4"}, "sdfxtp": {"description": "Scan delay flop, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sdfxtp", "library": "sky130_fd_sc_hd", "name": "sdfxtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfxtp"}, "and4bb": {"description": "4-input AND, first two inputs inverted.", "file_prefix": "sky130_fd_sc_hd__and4bb", "library": "sky130_fd_sc_hd", "name": "and4bb", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B_N", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and4bb"}, "macro_sparecell": {"description": "Macro cell for metal-mask-only revisioning, containing inverter, 2-input NOR, 2-input NAND, and constant cell.", "file_prefix": "sky130_fd_sc_hd__macro_sparecell", "library": "sky130_fd_sc_hd", "name": "macro_sparecell", "parameters": [], "ports": [["signal", "LO", "output", ""], ["power", "VGND", "input", "supply0"], ["power", "VNB", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VPWR", "input", "supply1"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__macro_sparecell"}, "dlymetal6s4s": {"description": "6-inverter delay with output from 4th inverter on horizontal route.", "file_prefix": "sky130_fd_sc_hd__dlymetal6s4s", "library": "sky130_fd_sc_hd", "name": "dlymetal6s4s", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlymetal6s4s"}, "nor4b": {"description": "4-input NOR, first input inverted.", "file_prefix": "sky130_fd_sc_hd__nor4b", "library": "sky130_fd_sc_hd", "name": "nor4b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor4b"}, "sdfbbp": {"description": "Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__sdfbbp", "library": "sky130_fd_sc_hd", "name": "sdfbbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "CLK", "input", ""], ["signal", "SET_B", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfbbp"}, "fahcon": {"description": "Full adder, inverted carry in, inverted carry out.", "file_prefix": "sky130_fd_sc_hd__fahcon", "library": "sky130_fd_sc_hd", "name": "fahcon", "parameters": [], "ports": [["signal", "COUT_N", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "CI", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fahcon"}, "or3b": {"description": "3-input OR, first input inverted.", "file_prefix": "sky130_fd_sc_hd__or3b", "library": "sky130_fd_sc_hd", "name": "or3b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or3b"}, "dlygate4sd3": {"description": "Delay Buffer 4-stage 0.50um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__dlygate4sd3", "library": "sky130_fd_sc_hd", "name": "dlygate4sd3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlygate4sd3"}, "dlxtn": {"description": "Delay latch, inverted enable, single output.", "file_prefix": "sky130_fd_sc_hd__dlxtn", "library": "sky130_fd_sc_hd", "name": "dlxtn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "D", "input", ""], ["signal", "GATE_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlxtn"}, "a221o": {"description": "2-input AND into first two inputs of 3-input OR.", "equation": "X = ((A1 & A2) | (B1 & B2) | C1)", "file_prefix": "sky130_fd_sc_hd__a221o", "library": "sky130_fd_sc_hd", "name": "a221o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a221o"}, "dfbbn": {"description": "Delay flop, inverted set, inverted reset, inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfbbn", "library": "sky130_fd_sc_hd", "name": "dfbbn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "CLK_N", "input", ""], ["signal", "SET_B", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfbbn"}, "ebufn": {"description": "Tri-state buffer, negative enable.", "file_prefix": "sky130_fd_sc_hd__ebufn", "library": "sky130_fd_sc_hd", "name": "ebufn", "parameters": [], "ports": [["signal", "Z", "output", ""], ["signal", "A", "input", ""], ["signal", "TE_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__ebufn"}, "bufbuf": {"description": "Double buffer.", "file_prefix": "sky130_fd_sc_hd__bufbuf", "library": "sky130_fd_sc_hd", "name": "bufbuf", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__bufbuf"}, "a2111oi": {"description": "2-input AND into first input of 4-input NOR.", "equation": "Y = !((A1 & A2) | B1 | C1 | D1)", "file_prefix": "sky130_fd_sc_hd__a2111oi", "library": "sky130_fd_sc_hd", "name": "a2111oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["signal", "D1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a2111oi"}, "a21bo": {"description": "2-input AND into first input of 2-input OR, 2nd input inverted.", "equation": "X = ((A1 & A2) | (!B1_N))", "file_prefix": "sky130_fd_sc_hd__a21bo", "library": "sky130_fd_sc_hd", "name": "a21bo", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a21bo"}, "o31a": {"description": "3-input OR into 2-input AND.", "equation": "X = ((A1 | A2 | A3) & B1)", "file_prefix": "sky130_fd_sc_hd__o31a", "library": "sky130_fd_sc_hd", "name": "o31a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o31a"}, "dlrbp": {"description": "Delay latch, inverted reset, non-inverted enable, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dlrbp", "library": "sky130_fd_sc_hd", "name": "dlrbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "RESET_B", "input", ""], ["signal", "D", "input", ""], ["signal", "GATE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlrbp"}, "o221a": {"description": "2-input OR into first two inputs of 3-input AND.", "equation": "X = ((A1 | A2) & (B1 | B2) & C1)", "file_prefix": "sky130_fd_sc_hd__o221a", "library": "sky130_fd_sc_hd", "name": "o221a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o221a"}, "o32ai": {"description": "3-input OR and 2-input OR into 2-input NAND.", "equation": "Y = !((A1 | A2 | A3) & (B1 | B2))", "file_prefix": "sky130_fd_sc_hd__o32ai", "library": "sky130_fd_sc_hd", "name": "o32ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o32ai"}, "a21oi": {"description": "2-input AND into first input of 2-input NOR.", "equation": "Y = !((A1 & A2) | B1)", "file_prefix": "sky130_fd_sc_hd__a21oi", "library": "sky130_fd_sc_hd", "name": "a21oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a21oi"}, "tapvgnd": {"description": "Tap cell with tap to ground, isolated power connection 1 row down.", "file_prefix": "sky130_fd_sc_hd__tapvgnd", "library": "sky130_fd_sc_hd", "name": "tapvgnd", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__tapvgnd"}, "sedfxtp": {"description": "Scan delay flop, data enable, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sedfxtp", "library": "sky130_fd_sc_hd", "name": "sedfxtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "DE", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sedfxtp"}, "lpflow_clkinvkapwr": {"description": "Clock tree inverter on keep-alive rail.", "file_prefix": "sky130_fd_sc_hd__lpflow_clkinvkapwr", "library": "sky130_fd_sc_hd", "name": "lpflow_clkinvkapwr", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["power", "KAPWR", "input", "supply1"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_clkinvkapwr"}, "ha": {"description": "Half adder.", "file_prefix": "sky130_fd_sc_hd__ha", "library": "sky130_fd_sc_hd", "name": "ha", "parameters": [], "ports": [["signal", "COUT", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__ha"}, "a21boi": {"description": "2-input AND into first input of 2-input NOR, 2nd input inverted.", "equation": "Y = !((A1 & A2) | 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"supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a311oi"}, "lpflow_inputiso0p": {"description": "Input isolator with non-inverted enable.", "equation": "X = (A & !SLEEP_B)", "file_prefix": "sky130_fd_sc_hd__lpflow_inputiso0p", "library": "sky130_fd_sc_hd", "name": "lpflow_inputiso0p", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "SLEEP", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputiso0p"}, "a32o": {"description": "3-input AND into first input, and 2-input AND into 2nd input of 2-input OR.", "equation": "X = ((A1 & A2 & A3) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a32o", "library": "sky130_fd_sc_hd", "name": "a32o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a32o"}, "lpflow_clkbufkapwr": {"description": "Clock tree buffer on keep-alive power rail.", "file_prefix": "sky130_fd_sc_hd__lpflow_clkbufkapwr", "library": "sky130_fd_sc_hd", "name": "lpflow_clkbufkapwr", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "KAPWR", "input", "supply1"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_clkbufkapwr"}, "mux2": {"description": "2-input multiplexer.", "file_prefix": "sky130_fd_sc_hd__mux2", "library": "sky130_fd_sc_hd", "name": "mux2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A0", "input", ""], ["signal", "A1", "input", ""], ["signal", "S", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__mux2"}, "a22o": {"description": "2-input AND into both inputs of 2-input OR.", "equation": "X = ((A1 & A2) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a22o", "library": "sky130_fd_sc_hd", "name": "a22o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a22o"}, "dlclkp": {"description": "Clock gate.", "file_prefix": "sky130_fd_sc_hd__dlclkp", "library": "sky130_fd_sc_hd", "name": "dlclkp", "parameters": [], "ports": [["signal", "GCLK", "output", ""], ["signal", "GATE", "input", ""], ["signal", "CLK", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlclkp"}, "fa": {"description": "Full adder.", "file_prefix": "sky130_fd_sc_hd__fa", "library": "sky130_fd_sc_hd", "name": "fa", "parameters": [], "ports": [["signal", "COUT", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "CIN", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fa"}, "o2111a": {"description": "2-input OR into first input of 4-input AND.", "equation": "X = ((A1 | A2) & B1 & C1 & D1)", "file_prefix": "sky130_fd_sc_hd__o2111a", "library": "sky130_fd_sc_hd", "name": "o2111a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["signal", "D1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o2111a"}, "or2": {"description": "2-input OR.", "file_prefix": "sky130_fd_sc_hd__or2", "library": "sky130_fd_sc_hd", "name": "or2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or2"}, "sdfrtp": {"description": "Scan delay flop, inverted reset, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sdfrtp", "library": "sky130_fd_sc_hd", "name": "sdfrtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfrtp"}, "nand2b": {"description": "2-input NAND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__nand2b", "library": "sky130_fd_sc_hd", "name": "nand2b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand2b"}, "lpflow_inputiso0n": {"description": "Input isolator with inverted enable.", "equation": "X = (A & SLEEP_B)", "file_prefix": "sky130_fd_sc_hd__lpflow_inputiso0n", "library": "sky130_fd_sc_hd", "name": "lpflow_inputiso0n", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "SLEEP_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputiso0n"}, "nand4b": {"description": "4-input NAND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__nand4b", "library": "sky130_fd_sc_hd", "name": "nand4b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand4b"}, "or4b": {"description": "4-input OR, first input inverted.", "file_prefix": "sky130_fd_sc_hd__or4b", "library": "sky130_fd_sc_hd", "name": "or4b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or4b"}, "dfrtp": {"description": "Delay flop, inverted reset, single output.", "file_prefix": "sky130_fd_sc_hd__dfrtp", "library": "sky130_fd_sc_hd", "name": "dfrtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfrtp"}, "o21ba": {"description": "2-input OR into first input of 2-input AND, 2nd input inverted.", "equation": "X = ((A1 | A2) & !B1_N)", "file_prefix": "sky130_fd_sc_hd__o21ba", "library": "sky130_fd_sc_hd", "name": "o21ba", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o21ba"}, "a21o": {"description": "2-input AND into first input of 2-input OR.", "equation": "X = ((A1 & A2) | B1)", "file_prefix": "sky130_fd_sc_hd__a21o", "library": "sky130_fd_sc_hd", "name": "a21o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a21o"}, "or2b": {"description": "2-input OR, first input inverted.", "file_prefix": "sky130_fd_sc_hd__or2b", "library": "sky130_fd_sc_hd", "name": "or2b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__or2b"}, "dlymetal6s2s": {"description": "6-inverter delay with output from 2nd stage on horizontal route.", "file_prefix": "sky130_fd_sc_hd__dlymetal6s2s", "library": "sky130_fd_sc_hd", "name": "dlymetal6s2s", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlymetal6s2s"}, "xnor3": {"description": "3-input exclusive NOR.", "file_prefix": "sky130_fd_sc_hd__xnor3", "library": "sky130_fd_sc_hd", "name": "xnor3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__xnor3"}, "dfbbp": {"description": "Delay flop, inverted set, inverted reset, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfbbp", "library": "sky130_fd_sc_hd", "name": "dfbbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "D", "input", ""], ["signal", "CLK", "input", ""], ["signal", "SET_B", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfbbp"}, "a211o": {"description": "2-input AND into first input of 3-input OR.", "equation": "X = ((A1 & A2) | B1 | C1)", "file_prefix": "sky130_fd_sc_hd__a211o", "library": "sky130_fd_sc_hd", "name": "a211o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a211o"}, "edfxbp": {"description": "Delay flop with loopback enable, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__edfxbp", "library": "sky130_fd_sc_hd", "name": "edfxbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "DE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__edfxbp"}, "sdfbbn": {"description": "Scan delay flop, inverted set, inverted reset, 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["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o22ai"}, "a2111o": {"description": "2-input AND into first input of 4-input OR.", "equation": "X = ((A1 & A2) | B1 | C1 | D1)", "file_prefix": "sky130_fd_sc_hd__a2111o", "library": "sky130_fd_sc_hd", "name": "a2111o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["signal", "D1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a2111o"}, "bufinv": {"description": "Buffer followed by inverter.", "file_prefix": "sky130_fd_sc_hd__bufinv", "library": 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"file_prefix": "sky130_fd_sc_hd__nand2", "library": "sky130_fd_sc_hd", "name": "nand2", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand2"}, "nand4": {"description": "4-input NAND.", "file_prefix": "sky130_fd_sc_hd__nand4", "library": "sky130_fd_sc_hd", "name": "nand4", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand4"}, "dlxbp": {"description": "Delay latch, non-inverted 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"supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o2bb2ai"}, "o32a": {"description": "3-input OR and 2-input OR into 2-input AND.", "equation": "X = ((A1 | A2 | A3) & (B1 | B2))", "file_prefix": "sky130_fd_sc_hd__o32a", "library": "sky130_fd_sc_hd", "name": "o32a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o32a"}, "lpflow_inputiso1p": {"description": "Input isolation, noninverted sleep.", "equation": "X = (A & !SLEEP)", "file_prefix": "sky130_fd_sc_hd__lpflow_inputiso1p", "library": "sky130_fd_sc_hd", "name": "lpflow_inputiso1p", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "SLEEP", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputiso1p"}, "and2b": {"description": "2-input AND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__and2b", "library": "sky130_fd_sc_hd", "name": "and2b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and2b"}, "clkdlybuf4s15": {"description": "Clock Delay Buffer 4-stage 0.15um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__clkdlybuf4s15", "library": "sky130_fd_sc_hd", "name": "clkdlybuf4s15", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkdlybuf4s15"}, "o21bai": {"description": "2-input OR into first input of 2-input NAND, 2nd iput inverted.", "equation": "Y = !((A1 | A2) & !B1_N)", "file_prefix": "sky130_fd_sc_hd__o21bai", "library": "sky130_fd_sc_hd", "name": "o21bai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o21bai"}, "and4": {"description": "4-input AND.", "file_prefix": "sky130_fd_sc_hd__and4", "library": "sky130_fd_sc_hd", "name": "and4", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and4"}, "o2111ai": {"description": "2-input OR into first input of 4-input NAND.", "equation": "Y = !((A1 | A2) & B1 & C1 & D1)", "file_prefix": "sky130_fd_sc_hd__o2111ai", "library": "sky130_fd_sc_hd", "name": "o2111ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["signal", "D1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o2111ai"}, "fah": {"description": "Full adder.", "file_prefix": "sky130_fd_sc_hd__fah", "library": "sky130_fd_sc_hd", "name": "fah", "parameters": [], "ports": [["signal", "COUT", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "CI", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fah"}, "inv": {"description": "Inverter.", "file_prefix": "sky130_fd_sc_hd__inv", "library": "sky130_fd_sc_hd", "name": "inv", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__inv"}, "xor3": {"description": "3-input exclusive OR.", "equation": "X = A ^ B ^ C", "file_prefix": "sky130_fd_sc_hd__xor3", "library": "sky130_fd_sc_hd", "name": "xor3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__xor3"}, "dlrtn": {"description": "Delay latch, inverted reset, inverted enable, single output.", "file_prefix": "sky130_fd_sc_hd__dlrtn", "library": "sky130_fd_sc_hd", "name": "dlrtn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "RESET_B", "input", ""], ["signal", "D", "input", ""], ["signal", "GATE_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlrtn"}, "nor2b": {"description": "2-input NOR, first input inverted.", "equation": "Y = !(A | B | C | !D)", "file_prefix": "sky130_fd_sc_hd__nor2b", "library": "sky130_fd_sc_hd", "name": "nor2b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor2b"}, "o41ai": {"description": "4-input OR into 2-input NAND.", "equation": "Y = !((A1 | A2 | A3 | A4) & B1)", "file_prefix": "sky130_fd_sc_hd__o41ai", "library": "sky130_fd_sc_hd", "name": "o41ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "A4", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o41ai"}, "and4b": {"description": "4-input AND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__and4b", "library": "sky130_fd_sc_hd", "name": "and4b", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and4b"}, "tapvpwrvgnd": {"description": "Substrate and well tap cell.", "file_prefix": "sky130_fd_sc_hd__tapvpwrvgnd", "library": "sky130_fd_sc_hd", "name": "tapvpwrvgnd", "parameters": [], "ports": [["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__tapvpwrvgnd"}, "a211oi": {"description": "2-input AND into first input of 3-input NOR.", "equation": "Y = !((A1 & A2) | B1 | C1)", "file_prefix": "sky130_fd_sc_hd__a211oi", "library": "sky130_fd_sc_hd", "name": "a211oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a211oi"}, "sdlclkp": {"description": "Scan gated clock.", "file_prefix": "sky130_fd_sc_hd__sdlclkp", "library": "sky130_fd_sc_hd", "name": "sdlclkp", "parameters": [], "ports": [["signal", "GCLK", "output", ""], ["signal", "SCE", "input", ""], ["signal", "GATE", "input", ""], ["signal", "CLK", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdlclkp"}, "and3": {"description": "3-input AND.", "file_prefix": "sky130_fd_sc_hd__and3", "library": "sky130_fd_sc_hd", "name": "and3", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and3"}, "nor3": {"description": "3-input NOR.", "equation": "Y = !(A | B | C | !D)", "file_prefix": "sky130_fd_sc_hd__nor3", "library": "sky130_fd_sc_hd", "name": "nor3", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor3"}, "a31oi": {"description": "3-input AND into first input of 2-input NOR.", "equation": "Y = !((A1 & A2 & A3) | B1)", "file_prefix": "sky130_fd_sc_hd__a31oi", "library": "sky130_fd_sc_hd", "name": "a31oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a31oi"}, "dfstp": {"description": "Delay flop, inverted set, single output.", "file_prefix": "sky130_fd_sc_hd__dfstp", "library": "sky130_fd_sc_hd", "name": "dfstp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfstp"}, "nor2": {"description": "2-input NOR.", "file_prefix": "sky130_fd_sc_hd__nor2", "library": "sky130_fd_sc_hd", "name": "nor2", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor2"}, "edfxtp": {"description": "Delay flop with loopback enable, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__edfxtp", "library": "sky130_fd_sc_hd", "name": "edfxtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "DE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__edfxtp"}, "o21ai": {"description": "2-input OR into first input of 2-input NAND.", "equation": "Y = !((A1 | A2) & B1)", "file_prefix": "sky130_fd_sc_hd__o21ai", "library": "sky130_fd_sc_hd", "name": "o21ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o21ai"}, "lpflow_isobufsrckapwr": {"description": "Input isolation, noninverted sleep on keep-alive power rail.", "equation": "X = (!A | SLEEP)", "file_prefix": "sky130_fd_sc_hd__lpflow_isobufsrckapwr", "library": "sky130_fd_sc_hd", "name": "lpflow_isobufsrckapwr", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "SLEEP", "input", ""], ["signal", "A", "input", ""], ["power", "KAPWR", "input", "supply1"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_isobufsrckapwr"}, "dlygate4sd2": {"description": "Delay Buffer 4-stage 0.18um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__dlygate4sd2", "library": "sky130_fd_sc_hd", "name": "dlygate4sd2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlygate4sd2"}, "clkbuf": {"description": "Clock tree buffer.", "file_prefix": "sky130_fd_sc_hd__clkbuf", "library": "sky130_fd_sc_hd", "name": "clkbuf", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkbuf"}, "buf": {"description": "Buffer.", "file_prefix": "sky130_fd_sc_hd__buf", "library": "sky130_fd_sc_hd", "name": "buf", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__buf"}, "diode": {"description": "Antenna tie-down diode.", "file_prefix": "sky130_fd_sc_hd__diode", "library": "sky130_fd_sc_hd", "name": "diode", "parameters": [], "ports": [["signal", "DIODE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__diode"}, "lpflow_inputisolatch": {"description": "Latching input isolator with inverted enable.", "file_prefix": "sky130_fd_sc_hd__lpflow_inputisolatch", "library": "sky130_fd_sc_hd", "name": "lpflow_inputisolatch", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "D", "input", ""], ["signal", "SLEEP_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputisolatch"}, "a22oi": {"description": "2-input AND into both inputs of 2-input NOR.", "equation": "Y = !((A1 & A2) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a22oi", "library": "sky130_fd_sc_hd", "name": "a22oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a22oi"}, "nand3b": {"description": "3-input NAND, first input inverted.", "file_prefix": "sky130_fd_sc_hd__nand3b", "library": "sky130_fd_sc_hd", "name": "nand3b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand3b"}, "einvn": {"description": "Tri-state inverter, negative enable.", "file_prefix": "sky130_fd_sc_hd__einvn", "library": "sky130_fd_sc_hd", "name": "einvn", "parameters": [], "ports": [["signal", "Z", "output", ""], ["signal", "A", "input", ""], ["signal", "TE_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__einvn"}, "nor4": {"description": "4-input NOR.", "equation": "Y = !(A | B | C | D)", "file_prefix": "sky130_fd_sc_hd__nor4", "library": "sky130_fd_sc_hd", "name": "nor4", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor4"}, "dfsbp": {"description": "Delay flop, inverted set, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfsbp", "library": "sky130_fd_sc_hd", "name": "dfsbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfsbp"}, "a222oi": {"description": "2-input AND into all inputs of 3-input NOR.", "equation": "Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))", "file_prefix": "sky130_fd_sc_hd__a222oi", "library": "sky130_fd_sc_hd", "name": "a222oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["signal", "C2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a222oi"}, "o21a": {"description": "2-input OR into first input of 2-input AND.", "equation": "X = ((A1 | A2) & B1)", "file_prefix": "sky130_fd_sc_hd__o21a", "library": "sky130_fd_sc_hd", "name": "o21a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o21a"}, "o211ai": {"description": "2-input OR into first input of 3-input NAND.", "equation": "Y = !((A1 | A2) & B1 & C1)", "file_prefix": "sky130_fd_sc_hd__o211ai", "library": "sky130_fd_sc_hd", "name": "o211ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o211ai"}, "lpflow_isobufsrc": {"description": "Input isolation, noninverted sleep.", "equation": "X = (!A | SLEEP)", "file_prefix": "sky130_fd_sc_hd__lpflow_isobufsrc", "library": "sky130_fd_sc_hd", "name": "lpflow_isobufsrc", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "SLEEP", "input", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_isobufsrc"}, "dfxbp": {"description": "Delay flop, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__dfxbp", "library": "sky130_fd_sc_hd", "name": "dfxbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dfxbp"}, "lpflow_inputiso1n": {"description": "Input isolation, inverted sleep.", "equation": "X = (A & SLEEP_B)", "file_prefix": "sky130_fd_sc_hd__lpflow_inputiso1n", "library": "sky130_fd_sc_hd", "name": "lpflow_inputiso1n", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "SLEEP_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_inputiso1n"}, "sdfrtn": {"description": "Scan delay flop, inverted reset, inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sdfrtn", "library": "sky130_fd_sc_hd", "name": "sdfrtn", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK_N", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "RESET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfrtn"}, "probec_p": {"description": "Virtual current probe point.", "file_prefix": "sky130_fd_sc_hd__probec_p", "library": "sky130_fd_sc_hd", "name": "probec_p", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VGND", "input", "supply0"], ["power", "VNB", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VPWR", "input", "supply1"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__probec_p"}, "fahcin": {"description": "Full adder, inverted carry in.", "file_prefix": "sky130_fd_sc_hd__fahcin", "library": "sky130_fd_sc_hd", "name": "fahcin", "parameters": [], "ports": [["signal", "COUT", "output", ""], ["signal", "SUM", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "CIN", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__fahcin"}, "clkinv": {"description": "Clock tree inverter.", "file_prefix": "sky130_fd_sc_hd__clkinv", "library": "sky130_fd_sc_hd", "name": "clkinv", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkinv"}, "a32oi": {"description": "3-input AND into first input, and 2-input AND into 2nd input of 2-input NOR.", "equation": "Y = !((A1 & A2 & A3) | (B1 & B2))", "file_prefix": "sky130_fd_sc_hd__a32oi", "library": "sky130_fd_sc_hd", "name": "a32oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a32oi"}, "lpflow_lsbuf_lh_isowell": {"description": "Level-shift buffer, low-to-high, isolated well on input buffer, no taps, double-row-height cell.", "file_prefix": "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell", "library": "sky130_fd_sc_hd", "name": "lpflow_lsbuf_lh_isowell", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "LOWLVPWR", "input", "wire"], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell"}, "dlymetal6s6s": {"description": "6-inverter delay with output from 6th inverter on horizontal route.", "file_prefix": "sky130_fd_sc_hd__dlymetal6s6s", "library": "sky130_fd_sc_hd", "name": "dlymetal6s6s", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlymetal6s6s"}, "o41a": {"description": "4-input OR into 2-input AND.", "equation": "X = ((A1 | A2 | A3 | A4) & B1)", "file_prefix": "sky130_fd_sc_hd__o41a", "library": "sky130_fd_sc_hd", "name": "o41a", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "A4", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o41a"}, "sdfstp": {"description": "Scan delay flop, inverted set, non-inverted clock, single output.", "file_prefix": "sky130_fd_sc_hd__sdfstp", "library": "sky130_fd_sc_hd", "name": "sdfstp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["signal", "SET_B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sdfstp"}, "dlrtp": {"description": "Delay latch, inverted reset, non-inverted enable, single output.", "file_prefix": "sky130_fd_sc_hd__dlrtp", "library": "sky130_fd_sc_hd", "name": "dlrtp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "RESET_B", "input", ""], ["signal", "D", "input", ""], ["signal", "GATE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__dlrtp"}, "sedfxbp": {"description": "Scan delay flop, data enable, non-inverted clock, complementary outputs.", "file_prefix": "sky130_fd_sc_hd__sedfxbp", "library": "sky130_fd_sc_hd", "name": "sedfxbp", "parameters": [], "ports": [["signal", "Q", "output", ""], ["signal", "Q_N", "output", ""], ["signal", "CLK", "input", ""], ["signal", "D", "input", ""], ["signal", "DE", "input", ""], ["signal", "SCD", "input", ""], ["signal", "SCE", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__sedfxbp"}, "lpflow_bleeder": {"description": "Current bleeder (weak pulldown to ground).", "file_prefix": "sky130_fd_sc_hd__lpflow_bleeder", "library": "sky130_fd_sc_hd", "name": "lpflow_bleeder", "parameters": [], "ports": [["signal", "SHORT", "input", ""], ["power", "VPWR", "inout", "wire"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__lpflow_bleeder"}, "nor4bb": {"description": "4-input NOR, first two inputs inverted.", "file_prefix": "sky130_fd_sc_hd__nor4bb", "library": "sky130_fd_sc_hd", "name": "nor4bb", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C_N", "input", ""], ["signal", "D_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor4bb"}, "clkdlybuf4s18": {"description": "Clock Delay Buffer 4-stage 0.18um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__clkdlybuf4s18", "library": "sky130_fd_sc_hd", "name": "clkdlybuf4s18", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkdlybuf4s18"}, "xor2": {"description": "2-input exclusive OR.", "equation": "X = A ^ B", "file_prefix": "sky130_fd_sc_hd__xor2", "library": "sky130_fd_sc_hd", "name": "xor2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__xor2"}, "and2": {"description": "2-input AND.", "file_prefix": "sky130_fd_sc_hd__and2", "library": "sky130_fd_sc_hd", "name": "and2", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__and2"}, "clkdlybuf4s25": {"description": "Clock Delay Buffer 4-stage 0.25um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__clkdlybuf4s25", "library": "sky130_fd_sc_hd", "name": "clkdlybuf4s25", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkdlybuf4s25"}, "a41o": {"description": "4-input AND into first input of 2-input OR.", "equation": "X = ((A1 & A2 & A3 & A4) | B1)", "file_prefix": "sky130_fd_sc_hd__a41o", "library": "sky130_fd_sc_hd", "name": "a41o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "A4", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a41o"}, "nand4bb": {"description": "4-input NAND, first two inputs inverted.", "file_prefix": "sky130_fd_sc_hd__nand4bb", "library": "sky130_fd_sc_hd", "name": "nand4bb", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A_N", "input", ""], ["signal", "B_N", "input", ""], ["signal", "C", "input", ""], ["signal", "D", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nand4bb"}, "mux2i": {"description": "2-input multiplexer, output inverted.", "file_prefix": "sky130_fd_sc_hd__mux2i", "library": "sky130_fd_sc_hd", "name": "mux2i", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A0", "input", ""], ["signal", "A1", "input", ""], ["signal", "S", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__mux2i"}, "o221ai": {"description": "2-input OR into first two inputs of 3-input NAND.", "equation": "Y = !((A1 | A2) & (B1 | B2) & C1)", "file_prefix": "sky130_fd_sc_hd__o221ai", "library": "sky130_fd_sc_hd", "name": "o221ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "B1", "input", ""], ["signal", "B2", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o221ai"}, "xnor2": {"description": "2-input exclusive NOR.", "equation": "Y = !(A ^ B)", "file_prefix": "sky130_fd_sc_hd__xnor2", "library": "sky130_fd_sc_hd", "name": "xnor2", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__xnor2"}, "o311ai": {"description": "3-input OR into 3-input NAND.", "equation": "Y = !((A1 | A2 | A3) & B1 & C1)", "file_prefix": "sky130_fd_sc_hd__o311ai", "library": "sky130_fd_sc_hd", "name": "o311ai", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__o311ai"}, "nor3b": {"description": "3-input NOR, first input inverted.", "equation": "Y = (!(A | B)) & !C)", "file_prefix": "sky130_fd_sc_hd__nor3b", "library": "sky130_fd_sc_hd", "name": "nor3b", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A", "input", ""], ["signal", "B", "input", ""], ["signal", "C_N", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__nor3b"}, "a311o": {"description": "3-input AND into first input of 3-input OR.", "equation": "X = ((A1 & A2 & A3) | B1 | C1)", "file_prefix": "sky130_fd_sc_hd__a311o", "library": "sky130_fd_sc_hd", "name": "a311o", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "B1", "input", ""], ["signal", "C1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a311o"}, "clkdlybuf4s50": {"description": "Clock Delay Buffer 4-stage 0.59um length inner stage gates.", "file_prefix": "sky130_fd_sc_hd__clkdlybuf4s50", "library": "sky130_fd_sc_hd", "name": "clkdlybuf4s50", "parameters": [], "ports": [["signal", "X", "output", ""], ["signal", "A", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__clkdlybuf4s50"}, "a41oi": {"description": "4-input AND into first input of 2-input NOR.", "equation": "Y = !((A1 & A2 & A3 & A4) | B1)", "file_prefix": "sky130_fd_sc_hd__a41oi", "library": "sky130_fd_sc_hd", "name": "a41oi", "parameters": [], "ports": [["signal", "Y", "output", ""], ["signal", "A1", "input", ""], ["signal", "A2", "input", ""], ["signal", "A3", "input", ""], ["signal", "A4", "input", ""], ["signal", "B1", "input", ""], ["power", "VPWR", "input", "supply1"], ["power", "VGND", "input", "supply0"], ["power", "VPB", "input", "supply1"], ["power", "VNB", "input", "supply0"]], "type": "cell", "verilog_name": "sky130_fd_sc_hd__a41oi"}} \ No newline at end of file diff --git a/docs/project_header.md b/docs/project_header.md new file mode 100644 index 0000000..4ff5180 --- /dev/null +++ b/docs/project_header.md @@ -0,0 +1,11 @@ +--- +documentclass: scrartcl +geometry: margin=2cm +fontsize: 14pt +mainfont: Latin Modern Sans +header-includes: +- \hypersetup{colorlinks=false, + allbordercolors={0 0 0}, + pdfborderstyle={/S/U/W 1}} +--- + diff --git a/docs/project_preview.md b/docs/project_preview.md new file mode 100644 index 0000000..c70cc8f --- /dev/null +++ b/docs/project_preview.md @@ -0,0 +1,30 @@ +## {title} + +{picture_link} + +* Author: {author} +* Description: {description} +* [Extra docs]({doc_link}) +* Clock: {clock_hz} Hz +* External hardware: {external_hw} + +### How it works + +{how_it_works} + +### How to test + +{how_to_test} + +### IO + +| # | Input | Output | +|---|--------------|--------------| +| 0 | {inputs[0]} | {outputs[0]} | +| 1 | {inputs[1]} | {outputs[1]} | +| 2 | {inputs[2]} | {outputs[2]} | +| 3 | {inputs[3]} | {outputs[3]} | +| 4 | {inputs[4]} | {outputs[4]} | +| 5 | {inputs[5]} | {outputs[5]} | +| 6 | {inputs[6]} | {outputs[6]} | +| 7 | {inputs[7]} | {outputs[7]} | diff --git a/documentation.py b/documentation.py new file mode 100644 index 0000000..c8e590e --- /dev/null +++ b/documentation.py @@ -0,0 +1,59 @@ +import logging +import re +import subprocess +import os + + +# documentation +def check_yaml_docs(yaml): + logging.info("checking docs") + for key in ['author', 'title', 'description', 'how_it_works', 'how_to_test', 'language']: + if key not in yaml['documentation']: + logging.error("missing key {} in documentation".format(key)) + exit(1) + if yaml['documentation'][key] == "": + logging.error("missing value for {} in documentation".format(key)) + exit(1) + + # if provided, check discord handle is valid + if len(yaml['documentation']['discord']): + parts = yaml['documentation']['discord'].split('#') + if len(parts) != 2 or len(parts[0]) == 0 or not re.match('^[0-9]{4}$', parts[1]): + logging.error('Invalid format for discord username') + exit(1) + + +def create_pdf(yaml): + yaml = yaml['documentation'] + logging.info("creating pdf") + script_dir = os.path.dirname(os.path.realpath(__file__)) + with open(os.path.join(script_dir, "docs/project_header.md")) as fh: + doc_header = fh.read() + with open(os.path.join(script_dir, "docs/project_preview.md")) as fh: + doc_template = fh.read() + + with open('datasheet.md', 'w') as fh: + fh.write(doc_header) + # handle pictures + yaml['picture_link'] = '' + if yaml['picture']: + # skip SVG for now, not supported by pandoc + picture_name = yaml['picture'] + if 'svg' not in picture_name: + yaml['picture_link'] = '![picture]({})'.format(picture_name) + else: + logging.warning("svg not supported") + + # now build the doc & print it + try: + doc = doc_template.format(**yaml) + fh.write(doc) + fh.write("\n\pagebreak\n") + except IndexError: + logging.warning("missing pins in info.yaml, skipping") + + pdf_cmd = 'pandoc --pdf-engine=xelatex -i datasheet.md -o datasheet.pdf' + logging.info(pdf_cmd) + p = subprocess.run(pdf_cmd, shell=True) + if p.returncode != 0: + logging.error("pdf command failed") diff --git a/lint.sh b/lint.sh new file mode 100755 index 0000000..983de92 --- /dev/null +++ b/lint.sh @@ -0,0 +1 @@ +flake8 --ignore E203,E123,E501,E221,E401,W605 documentation.py project.py tt_tool.py reports.py diff --git a/project.py b/project.py new file mode 100644 index 0000000..240fd1e --- /dev/null +++ b/project.py @@ -0,0 +1,97 @@ +import yaml +import logging +import requests +import os + + +def load_yaml(args): + with open(args.yaml, "r") as stream: + return (yaml.safe_load(stream)) + + +def create_user_config(yaml): + logging.info("creating include file") + sources = get_project_source(yaml) + top_module = get_top_module(yaml) + + if top_module == 'top': + logging.error("top module cannot be called top - prepend your repo name to make it unique") + exit(1) + + filename = 'user_config.tcl' + with open(os.path.join('src', filename), 'w') as fh: + fh.write("set ::env(DESIGN_NAME) {}\n".format(top_module)) + fh.write('set ::env(VERILOG_FILES) "\\\n') + for line, source in enumerate(sources): + fh.write(" $::env(DESIGN_DIR)/" + source) + if line != len(sources) - 1: + fh.write(' \\\n') + fh.write('"\n') + + +def fetch_file(url, filename): + logging.info("trying to download {}".format(url)) + r = requests.get(url) + if r.status_code != 200: + logging.warning("couldn't download {}".format(url)) + exit(1) + + with open(filename, 'wb') as fh: + logging.info("written to {}".format(filename)) + fh.write(r.content) + + +def get_project_source(yaml): + # wokwi_id must be an int or 0 + try: + wokwi_id = int(yaml['project']['wokwi_id']) + except ValueError: + logging.error("wokwi id must be an integer") + exit(1) + + # it's a wokwi project + if wokwi_id != 0: + url = "https://wokwi.com/api/projects/{}/verilog".format(wokwi_id) + src_file = "user_module_{}.v".format(wokwi_id) + fetch_file(url, os.path.join("src", src_file)) + + # also fetch the wokwi diagram + url = "https://wokwi.com/api/projects/{}/diagram.json".format(wokwi_id) + diagram_file = "wokwi_diagram.json" + fetch_file(url, os.path.join("src", diagram_file)) + + return [src_file, 'cells.v'] + + # else it's HDL, so check source files + else: + if 'source_files' not in yaml['project']: + logging.error("source files must be provided if wokwi_id is set to 0") + exit(1) + + source_files = yaml['project']['source_files'] + if source_files is None: + logging.error("must be more than 1 source file") + exit(1) + + if len(source_files) == 0: + logging.error("must be more than 1 source file") + exit(1) + + if 'top_module' not in yaml['project']: + logging.error("must provide a top module name") + exit(1) + + for filename in source_files: + if not os.path.exists(os.path.join('src', filename)): + logging.error(f"{filename} doesn't exist in the repo") + exit(1) + + return source_files + + +def get_top_module(yaml): + wokwi_id = int(yaml['project']['wokwi_id']) + if wokwi_id != 0: + return "user_module_{}".format(wokwi_id) + else: + return yaml['project']['top_module'] diff --git a/reports.py b/reports.py new file mode 100755 index 0000000..bacae1b --- /dev/null +++ b/reports.py @@ -0,0 +1,116 @@ +import os +import csv +import json +import re +import glob + +# can't find a google version +CELL_URL = 'https://antmicro-skywater-pdk-docs.readthedocs.io/en/test-submodules-in-rtd/contents/libraries/sky130_fd_sc_ls/cells/' + + +def print_warnings(args): + warnings = [] + with open(os.path.join(args.run_dir, 'logs/synthesis/1-synthesis.log')) as f: + for line in f.readlines(): + if line.startswith('Warning:'): + # bogus warning https://github.com/YosysHQ/yosys/commit/bfacaddca8a2e113e4bc3d6177612ccdba1555c8 + if 'WIDTHLABEL' not in line: + warnings.append(line.strip()) + if len(warnings): + print('# Synthesis warnings') + print() + for warning in warnings: + print(f'* {warning}') + + +def print_stats(args): + with open(os.path.join(args.run_dir, 'reports/metrics.csv')) as f: + report = list(csv.DictReader(f))[0] + + print('# Routing stats') + print() + print('| Utilisation | Wire length (um) |') + print('|-------------|------------------|') + print('| {} | {} |'.format(report['OpenDP_Util'], report['wire_length'])) + + +# Print the summaries +def summarize(args): + cell_count = get_cell_count_from_gl(args) + script_dir = os.path.dirname(os.path.realpath(__file__)) + + with open(os.path.join(script_dir, 'categories.json')) as fh: + categories = json.load(fh) + with open(os.path.join(script_dir, 'defs.json')) as fh: + defs = json.load(fh) + + # print all used cells, sorted by frequency + total = 0 + if args.print_cell_summary: + print('# Cell usage') + print() + print('| Cell Name | Description | Count |') + print('|-----------|-------------|-------|') + for name, count in sorted(cell_count.items(), key=lambda item: item[1], reverse=True): + if count > 0: + total += count + cell_link = f'{CELL_URL}{name}' + print(f'| [{name}]({cell_link}) | {defs[name]["description"]} |{count} |') + + print(f'| | Total | {total} |') + + if args.print_cell_category: + by_category = {} + for cell_name in cell_count: + cat_index = categories['map'][cell_name] + cat_name = categories['categories'][cat_index] + if cat_name in by_category: + by_category[cat_name]['count'] += cell_count[cell_name] + by_category[cat_name]['examples'].append(cell_name) + else: + by_category[cat_name] = {'count' : cell_count[cell_name], 'examples' : [cell_name]} + + print('# Cell usage by Category') + print() + print('| Category | Cells | Count |') + print('|---------------|----------|-------|') + for cat_name, cat_dict in sorted(by_category.items(), key=lambda x: x[1]['count'], reverse=True): + cell_links = [f'[{name}]({CELL_URL}{name})' for name in cat_dict['examples']] + print(f'|{cat_name} | {" ".join(cell_links)} | {cat_dict["count"]}|') + + +# Parse the lib, cell and drive strength an OpenLane gate-level Verilog file +def get_cell_count_from_gl(args): + cell_count = {} + total = 0 + gl_files = glob.glob(os.path.join(args.run_dir, 'results/final/verilog/gl/*.nl.v')) + with open(gl_files[0]) as fh: + for line in fh.readlines(): + m = re.search(r'sky130_(\S+)__(\S+)_(\d+)', line) + if m is not None: + total += 1 + cell_lib = m.group(1) + cell_name = m.group(2) + cell_drive = m.group(3) + assert cell_lib in ['fd_sc_hd', 'ef_sc_hd'] + assert int(cell_drive) > 0 + try: + cell_count[cell_name] += 1 + except KeyError: + cell_count[cell_name] = 1 + return (cell_count) + + +# Load all the json defs and combine into one big dict, keyed by cellname +# Needs access to the PDK +def create_defs(args): + # replace this with a find + json_files = glob.glob('sky130_fd_sc_hd/latest/cells/*/definition.json') + definitions = {} + for json_file in json_files: + with open(json_file) as fh: + definition = json.load(fh) + definitions[definition['name']] = definition + + with open('defs.json', 'w') as fh: + json.dump(definitions, fh) diff --git a/tt_tool.py b/tt_tool.py new file mode 100755 index 0000000..86935e9 --- /dev/null +++ b/tt_tool.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python3 +import sys +import logging +import argparse +import documentation +import project +import reports + +if __name__ == '__main__': + parser = argparse.ArgumentParser(description="TT setup") + parser.add_argument('--yaml', help="the project's yaml configuration file", default='info.yaml') + parser.add_argument('--run-dir', help="OpenLane run directory", default='runs/wokwi') # set in the github action yaml + parser.add_argument('--debug', help="debug logging", action="store_const", dest="loglevel", const=logging.DEBUG, default=logging.INFO) + + # tests & checks + parser.add_argument('--check-docs', help="check the documentation part of the yaml", action="store_const", const=True) + + # reports & summaries + parser.add_argument('--create-cell-defs', help="create def file", action="store_const", const=True, default=False) + parser.add_argument('--print-cell-summary', help="print summary", action="store_const", const=True, default=False) + parser.add_argument('--print-cell-category', help="print category", action="store_const", const=True, default=False) + parser.add_argument('--print-stats', help="print some stats from the run", action="store_const", const=True) + parser.add_argument('--print-warnings', help="print any warnings", action="store_const", const=True) + + # documentation + parser.add_argument('--create-project-pdf', help="create a single page PDF", action="store_const", const=True) + + # configure + parser.add_argument('--create-user-config', help="create the user_config.tcl file with top module and source files", action="store_const", const=True) + + args = parser.parse_args() + + # setup log + log_format = logging.Formatter('%(asctime)s - %(module)-10s - %(levelname)-8s - %(message)s') + # configure the client logging + log = logging.getLogger('') + # has to be set to debug as is the root logger + log.setLevel(args.loglevel) + + # create console handler and set level to info + ch = logging.StreamHandler(sys.stdout) + # create formatter for console + ch.setFormatter(log_format) + log.addHandler(ch) + + project_yaml = project.load_yaml(args) + + # handle the options + if args.check_docs: + documentation.check_yaml_docs(project_yaml) + + elif args.print_cell_summary or args.print_cell_category: + reports.summarize(args) + + elif args.create_cell_defs: + reports.create_defs(args) + + elif args.print_stats: + reports.print_stats(args) + + elif args.print_warnings: + reports.print_warnings(args) + + elif args.create_user_config: + project.create_user_config(project_yaml) + + elif args.create_project_pdf: + documentation.create_pdf(project_yaml) + + else: + parser.print_help()