From 40060b69d273590e0ec4b8d67e01dbc05b6ae487 Mon Sep 17 00:00:00 2001
From: Matt Venn <matt@mattvenn.net>
Date: Wed, 26 Apr 2023 17:40:22 +0200
Subject: [PATCH] fix wirelength

---
 docs/hugo_index_template.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/hugo_index_template.md b/docs/hugo_index_template.md
index 4ce62e8..c08317f 100644
--- a/docs/hugo_index_template.md
+++ b/docs/hugo_index_template.md
@@ -26,7 +26,7 @@ description: 249 designs, closed 24th April 2023
 * total cells 79674
 * max cells 1287 for [project 072](./072)
 * max utilisation 59.95% for [project 044](./044)
-* total wire length 4079353mm
+* total wire length 4079 mm
 * 94 used Wokwi, 135 Verilog, 1 myhdl, 7 Amaranth, spade 1, xls 2, migen 1, systemverilog 3, mixed radix circuit synthesis (mrcs) 1, chisel 1.
 * top 10 tags:
     - test      : 21