mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
feat(precheck): add analog pin check for ihp-sg13g2
This commit is contained in:
htfab
+28
-21
@@ -17,10 +17,9 @@ from klayout_tools import parse_lyp_layers
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from pin_check import pin_check
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from precheck_failure import PrecheckFailure
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from tech_data import (
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analog_pin_pos,
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analog_pin_rects,
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boundary_layer,
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forbidden_layers,
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layer_map,
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lyp_filename,
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tech_names,
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valid_layers,
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@@ -261,42 +260,50 @@ def analog_pin_check(
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if is_analog:
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lib = gdstk.read_gds(gds)
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top = lib.top_level()[0]
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met4 = top.copy("test_met4")
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met4.flatten()
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met4.filter([layer_map[tech]["met4"]], False)
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via3 = top.copy("test_via3")
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via3.flatten()
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via3.filter([layer_map[tech]["via3"]], False)
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filtered = {}
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for pin in range(8):
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x = analog_pin_pos[tech](pin, uses_3v3)
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pin_over = gdstk.rectangle((x, 0), (x + 0.9, 1.0))
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pin_around = gdstk.boolean(
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gdstk.offset(pin_over, 0.5), gdstk.offset(pin_over, 0.1), "not"
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for pin, (rect, pin_layer, via_layers) in enumerate(
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analog_pin_rects(tech, uses_3v3)
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):
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for layer in [pin_layer] + via_layers:
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if layer not in filtered:
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i = len(filtered)
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lf = top.copy(f"test_lf_{i}")
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lf.flatten()
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lf.filter([layer], False)
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filtered[layer] = lf
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pin_rect = gdstk.rectangle(*rect)
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pin_ring = gdstk.boolean(
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gdstk.offset(pin_rect, 0.5), gdstk.offset(pin_rect, 0.1), "not"
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)
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via3_over = gdstk.boolean(via3.polygons, pin_over, "and")
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met4_around = gdstk.boolean(met4.polygons, pin_around, "and")
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connected = bool(via3_over) or bool(met4_around)
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pin_layer_polygons = filtered[pin_layer].polygons
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connected = bool(gdstk.boolean(pin_layer_polygons, pin_ring, "and"))
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for via_layer in via_layers:
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via_layer_polygons = filtered[via_layer].polygons
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connected = connected or bool(
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gdstk.boolean(via_layer_polygons, pin_rect, "and")
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)
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expected_pc = pin < analog_pins
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expected_pd = bool(pinout.get(f"ua[{pin}]", ""))
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if connected and not expected_pc:
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raise PrecheckFailure(
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f"Analog pin `ua[{pin}]` is connected to some metal but `analog_pins` is set to {analog_pins} in `info.yaml`. Either increase `analog_pins` to at least {pin+1}, or remove any metal4 or via3 adjacent to `ua[{pin}]`."
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f"Analog pin `ua[{pin}]` is connected to some metal but `analog_pins` is set to {analog_pins} in `info.yaml`. Either increase `analog_pins` to at least {pin+1}, or remove any metal or via adjacent to `ua[{pin}]`."
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)
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elif connected and not expected_pd:
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raise PrecheckFailure(
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f"Analog pin `ua[{pin}]` is connected to some metal but the description of `ua[{pin}]` in the pinout section of `info.yaml` is empty. Either add a description or remove any metal4 or via3 adjacent to `ua[{pin}]`."
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f"Analog pin `ua[{pin}]` is connected to some metal but the description of `ua[{pin}]` in the pinout section of `info.yaml` is empty. Either add a description or remove any metal or via adjacent to `ua[{pin}]`."
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)
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elif not connected and expected_pc:
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raise PrecheckFailure(
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f"Analog pin `ua[{pin}]` is not connected to any adjacent metal but `analog_pins` is set to {analog_pins} in `info.yaml`. Either wire up `ua[{pin}]` to your design using metal4 or via3, or decrease `analog_pins` to {pin}."
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f"Analog pin `ua[{pin}]` is not connected to any adjacent metal but `analog_pins` is set to {analog_pins} in `info.yaml`. Either wire up `ua[{pin}]` to your design or decrease `analog_pins` to {pin}."
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)
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elif not connected and expected_pd:
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raise PrecheckFailure(
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f"Analog pin `ua[{pin}]` is not connected to any adjacent metal but the description of `ua[{pin}]` in the pinout section of `info.yaml` is non-empty. Either wire up `ua[{pin}]` to your design using metal4 or via3, or remove the description for the disconnected pin."
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f"Analog pin `ua[{pin}]` is not connected to any adjacent metal but the description of `ua[{pin}]` in the pinout section of `info.yaml` is non-empty. Either wire up `ua[{pin}]` to your design or remove the description for the disconnected pin."
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)
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@@ -437,7 +444,7 @@ def main():
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"check": lambda: analog_pin_check(
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gds_file, tech, is_analog, uses_3v3, analog_pins, pinout
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),
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"techs": ["sky130A"],
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"techs": ["sky130A", "ihp-sg13g2"],
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},
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]
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+29
-12
@@ -1,3 +1,5 @@
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tech_names = ["sky130A", "ihp-sg13g2", "gf180mcuD"]
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# fmt: off
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valid_layers_sky130A = [
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'cldntm.mask', 'ldntm.drawing', 'cncm.mask', 'ctunm.mask', 'cnwm.mask', 'cnsm.mask', 'cfom.drawing', 'cfom.maskAdd',
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@@ -93,15 +95,34 @@ valid_layers_gf180mcuD = [
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]
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# fmt: on
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# layers used for the analog pin check
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layer_map_sky130A = {
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"met4": (71, 20),
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"via3": (70, 44),
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}
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def analog_pin_pos_sky130A(pin_number: int, uses_3v3: bool):
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return 151.81 - 19.32 * pin_number - (15.64 if uses_3v3 else 0)
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def analog_pin_rects(tech: str, uses_3v3: bool):
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if tech == "sky130A":
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pin_layer = (71, 20) # met4
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via_layers = [(70, 44)] # via3
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for pin_number in range(8):
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if uses_3v3:
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x1, y1 = 136.17 - 19.32 * pin_number, 0.0
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else:
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x1, y1 = 151.81 - 19.32 * pin_number, 0.0
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x2, y2 = x1 + 0.9, y1 + 1.0
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rect = ((x1, y1), (x2, y2))
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yield (rect, pin_layer, via_layers)
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elif tech == "ihp-sg13g2":
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pin_layer = (126, 0) # TopMetal1
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via_layers = [(125, 0)] # TopVia1
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for pin_number in range(8):
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if uses_3v3:
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raise NotImplementedError
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else:
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x1, y1 = 190.165 - 24.48 * pin_number, 0.0
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x2, y2 = x1 + 1.75, y1 + 2.0
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rect = ((x1, y1), (x2, y2))
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yield (rect, pin_layer, via_layers)
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elif tech in tech_names:
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raise NotImplementedError
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else:
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raise ValueError(f"unexpected tech {tech}")
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valid_layers = {
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@@ -109,8 +130,6 @@ valid_layers = {
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"ihp-sg13g2": valid_layers_ihp_sg13g2,
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"gf180mcuD": valid_layers_gf180mcuD,
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}
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layer_map = {"sky130A": layer_map_sky130A}
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analog_pin_pos = {"sky130A": analog_pin_pos_sky130A}
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lyp_filename = {
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"sky130A": "sky130A.lyp",
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"ihp-sg13g2": "sg13g2.lyp",
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@@ -165,5 +184,3 @@ boundary_layer = {
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"ihp-sg13g2": "prBoundary.boundary",
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"gf180mcuD": "PR_bndry",
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}
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tech_names = ["sky130A", "ihp-sg13g2", "gf180mcuD"]
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