feat: generate gl includes for user projects

This enables running GL tests on the final GL netlist of the actual chip

project.py

@@ -67,9 +67,12 @@ class Project:
         except FileNotFoundError:
             self.metrics = {}
 
+    def is_chip_rom(self):
+        return self.get_macro_name() == "tt_um_chip_rom"
+
     def check_ports(self):
         top = self.get_macro_name()
-        if not self.is_user_project and top == "tt_um_chip_rom":
+        if not self.is_user_project and self.is_chip_rom():
             return  # Chip ROM is auto generated, so we don't have the verilog yet
         sources = [os.path.join(self.src_dir, src) for src in self.src_files]
         source_list = " ".join(sources)