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fix: temporary workaround for ua being 4 bits wide instead of 8
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+1
-1
@@ -214,7 +214,7 @@ class Project:
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]
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]
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if self.info.is_analog:
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if self.info.is_analog:
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required_ports += [
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required_ports += [
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["inout", "ua", 8],
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["inout", "ua", 4],
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]
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]
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if include_power_ports:
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if include_power_ports:
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required_ports += [
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required_ports += [
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