mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
feat(datasheet): add new pinouts
Add new pinouts for SKY130, IHP SG13G2 and GF180mcuD. Valid keys for `show_pinouts` can now be easily seen in the `pinout_map` dictionary: - `caravel` - `openframe` - `openframe_sky130` - `customframe_ihp_sg13g2` - `customframe_gf180mcud` The pinout chapter in the datasheet has also been reworked: the content now exists directly in the typst template instead of being an external file. This is to make use of the `pinout_map` and to allow for easier modification of the content. This change also allows the page to make use of the `callout` function.
This commit is contained in:
Kristaps Jurkans
committed by
Uri Shaked
Uri Shaked
parent
d9b4ee2345
commit
4afe8f6941
@@ -141,4 +141,265 @@
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$dagger$ Internally, there's no difference between `clk`, `rst_n` and `ui_in` pins. They are all just bits in the
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`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
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]
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}
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#let openframe_sky130 = {
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align(center,
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table(
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columns: 4,
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align: left,
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table.header(
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[QFN64 pin], [mprj_io_pin], [Function], [Signal]
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),
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`1`, `vssa2`, [Ground], [GND],
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`2`, `25`, [Output], `uo[1]`,
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`3`, `26`, [Output], `uo[2]`,
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`4`, `27`, [Output], `uo[3]`,
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`5`, `28`, [Output], `uo[4]`,
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`6`, `29`, [Output], `uo[5]`,
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`7`, `30`, [Output], `uo[6]`,
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`8`, `31`, [Output], `uo[7]`,
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`9`, `vdda2`, [Power], [VDD Analog],
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`10`, `vssd2`, [Ground], [GND],
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`11`, `32`, [Analog], `analog[6]`,
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`12`, `33`, [Analog], `analog[7]`,
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`13`, `34`, [Analog], `analog[8]`,
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`14`, `35`, [Analog], `analog[9]`,
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`15`, `36`, [Analog], `analog[10]`,
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`16`, `37`, [Analog], `analog[11]`,
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`17`, `vddio`, [Power], [VDD IO],
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`18`, `vccd`, [Power], [VDD Core],
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`19`, `NC`, [], [],
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`20`, `vssa`, [Ground], [GND],
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`21`, `resetb`, [], [],
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`22`, `38`, [Mux], `ctrl_ena`,
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`23`, `vssd`, [Ground], [GND],
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`24`, `39`, [Mux], `ctrl_sel_inc`,
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`25`, `40`, [Mux], `ctrl_sel_rst_n`,
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`26`, `41`, [Reserved], [(none)],
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`27`, `42`, [Reserved], [(none)],
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`28`, `43`, [Reserved], [(none)],
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`29`, `vssio`, [Ground], [GND],
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`30`, `vdda`, [Power], [VDD Analog],
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`31`, `0`, [Input], `ui[0]`,
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`32`, `1`, [Input], `ui[1]`,
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`33`, `2`, [Input], `ui[2]`,
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`34`, `3`, [Input], `ui[3]`,
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`35`, `4`, [Input], `ui[4]`,
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`36`, `5`, [Input], `ui[5]`,
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`37`, `6`, [Input], `ui[6]`,
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`38`, `vssa1`, [Ground], [GND],
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`39`, `vssd1`, [Ground], [GND],
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`40`, `vdda1`, [Power], [VDD Analog],
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`41`, `7`, [Analog], `analog[0]`,
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`42`, `8`, [Analog], `analog[1]`,
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`43`, `9`, [Analog], `analog[2]`,
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`44`, `10`, [Analog], `analog[3]`,
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`45`, `11`, [Analog], `analog[4]`,
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`46`, `12`, [Analog], `analog[5]`,
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`47`, `vdda1`, [Power], [VDD Analog],
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`48`, `13`, [Input], `ui[7]`,
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`49`, `vccd1`, [Power], [VDD Core],
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`50`, `14`, [Input], [`u_clk` $dagger$],
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`51`, `15`, [Input], [`u_rst_n` $dagger$],
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`52`, `vssa1`, [Ground], [GND],
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`53`, `16`, [Bidirectional], `io[0]`,
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`54`, `17`, [Bidirectional], `io[1]`,
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`55`, `18`, [Bidirectional], `io[2]`,
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`56`, `vssio`, [Ground], [GND],
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`57`, `19`, [Bidirectional], `io[3]`,
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`58`, `20`, [Bidirectional], `io[4]`,
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`59`, `21`, [Bidirectional], `io[5]`,
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`60`, `22`, [Bidirectional], `io[6]`,
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`61`, `23`, [Bidirectional], `io[7]`,
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`62`, `24`, [Output], `uo[0]`,
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`63`, `vccd2`, [Power], [VDD Core],
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`64`, `vddio`, [Power], [VDD IO],
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`EPAD`, [], [Ground], []
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)
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)
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[
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$dagger$ Internally, there's no difference between `u_clk`, `u_rst_n`, and `ui` pins. They are all just bits in the
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`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
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]
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}
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#let customframe_ihp_sg13g2 = {
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align(center,
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table(
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columns: 4,
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align: left,
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table.header(
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[Die Pad], [QFN64 pin], [Function], [Signal]
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),
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`0`, `1`, [Mux Control], `ctrl_ena`,
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`1`, `2`, [Mux Control], `ctrl_sel_inc`,
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`2`, `3`, [Mux Control], `ctrl_sel_rst_n`,
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`3`, `4`, [Reserved], [],
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`4`, `5`, [Reserved], [],
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`5`, `6`, [Reserved], [],
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`6`, `7`, [Reserved], [],
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`7`, `8`, [Reserved], [],
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`8`, `9`, [Output], `uo[0]`,
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`9`, `10`, [Output], `uo[1]`,
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`10`, `11`, [Output], `uo[2]`,
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`11`, `12`, [Output], `uo[3]`,
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`12`, `13`, [Output], `uo[4]`,
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`13`, `14`, [Output], `uo[5]`,
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`14`, `15`, [Output], `uo[6]`,
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`15`, `16`, [Output], `uo[7]`,
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`16`, `17`, [Power], [VDD IO],
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`17`, `18`, [Ground], [GND IO],
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`18`, `19`, [Analog], `analog[0]`,
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`19`, `20`, [Analog], `analog[1]`,
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`20`, `21`, [Analog], `analog[2]`,
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`21`, `22`, [Analog], `analog[3]`,
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`22`, `23`, [Power], [VDD Analog],
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`23`, `24`, [Ground], [GND Analog],
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`24`, `25`, [Analog], `analog[4]`,
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`25`, `26`, [Analog], `analog[5]`,
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`26`, `27`, [Analog], `analog[6]`,
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`27`, `28`, [Analog], `analog[7]`,
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`28`, `29`, [Ground], [GND Core],
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`29`, `30`, [Power], [VDD Core],
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`30`, `31`, [Ground], [GND IO],
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`31`, `32`, [Power], [VDD IO],
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`32`, `33`, [Bidirectional], `uio[0]`,
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`33`, `34`, [Bidirectional], `uio[1]`,
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`34`, `35`, [Bidirectional], `uio[2]`,
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`35`, `36`, [Bidirectional], `uio[3]`,
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`36`, `37`, [Bidirectional], `uio[4]`,
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`37`, `38`, [Bidirectional], `uio[5]`,
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`38`, `39`, [Bidirectional], `uio[6]`,
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`39`, `40`, [Bidirectional], `uio[7]`,
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`40`, `41`, [Input], `ui[0]`,
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`41`, `42`, [Input], `ui[1]`,
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`42`, `43`, [Input], `ui[2]`,
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`43`, `44`, [Input], `ui[3]`,
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`44`, `45`, [Input], `ui[4]`,
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`45`, `46`, [Input], `ui[5]`,
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`46`, `47`, [Input], `ui[6]`,
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`47`, `48`, [Input], `ui[7]`,
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`48`, `49`, [Input], [`u_rst_n` $dagger$],
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`49`, `50`, [Input], [`u_clk` $dagger$],
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`50`, `51`, [Ground], [GND IO],
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`51`, `52`, [Power], [VDD IO],
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`52`, `53`, [Analog], `analog[8]`,
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`53`, `54`, [Analog], `analog[9]`,
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`54`, `55`, [Analog], `analog[10]`,
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`55`, `56`, [Analog], `analog[11]`,
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`56`, `57`, [Ground], [GND Analog],
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`57`, `58`, [Power], [VDD Analog],
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`58`, `59`, [Analog], `analog[12]`,
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`59`, `60`, [Analog], `analog[13]`,
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`60`, `61`, [Analog], `analog[14]`,
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`61`, `62`, [Analog], `analog[15]`,
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`62`, `63`, [Ground], [GND Core],
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`63`, `64`, [Power], [VDD Core],
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`SUB`, `EPAD`, [Ground], [],
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)
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)
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[
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$dagger$ Internally, there's no difference between `u_clk`, `u_rst_n`, and `ui` pins. They are all just bits in the
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`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
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]
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}
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#let customframe_gf180mcud = {
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align(center,
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table(
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columns: 4,
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align: left,
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table.header(
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[Die Pad], [QFN64 pin], [Function], [Signal]
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),
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`0`, `1`, [Mux Control], `ctrl_ena`,
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`1`, `2`, [Mux Control], `ctrl_sel_inc`,
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`2`, `3`, [Mux Control], `ctrl_sel_rst_n`,
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`3`, `4`, [Reserved], [],
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`4`, `5`, [Reserved], [],
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`5`, `6`, [Reserved], [],
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`6`, `7`, [Reserved], [],
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`7`, `8`, [Reserved], [],
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`8`, `EPAD`, [Ground], [GND IO],
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`9`, `9`, [Output], `uo[0]`,
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`10`, `10`, [Output], `uo[1]`,
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`11`, `11`, [Output], `uo[2]`,
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`12`, `12`, [Output], `uo[3]`,
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`13`, `13`, [Output], `uo[4]`,
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`14`, `14`, [Output], `uo[5]`,
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`15`, `15`, [Output], `uo[6]`,
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`16`, `16`, [Output], `uo[7]`,
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`17`, `17`, [Power], [VDD IO],
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`18`, `EPAD`, [Ground], [GND IO],
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`19`, `18`, [Analog], `analog[0]`,
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`20`, `19`, [Analog], `analog[1]`,
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`21`, `20`, [Analog], `analog[2]`,
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`22`, `21`, [Analog], `analog[3]`,
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`23`, `22`, [Analog], `analog[4]`,
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`24`, `23`, [Analog], `analog[5]`,
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`25`, `24`, [Power], [PWR Analog],
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`26`, `EPAD`, [Ground], [GND Analog],
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`27`, `25`, [Analog], `analog[6]`,
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`28`, `26`, [Analog], `analog[7]`,
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`29`, `27`, [Analog], `analog[8]`,
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`30`, `28`, [Analog], `analog[9]`,
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`31`, `29`, [Analog], `analog[10]`,
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`32`, `30`, [Analog], `analog[11]`,
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`33`, `EPAD`, [Ground], [GND Core],
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`34`, `31`, [Power], [VDD Core],
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`35`, `EPAD`, [Ground], [GND IO],
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`36`, `32`, [Power], [VDD IO],
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`37`, `33`, [Bidirectional], `uio[0]`,
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`38`, `34`, [Bidirectional], `uio[1]`,
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`39`, `35`, [Bidirectional], `uio[2]`,
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`40`, `36`, [Bidirectional], `uio[3]`,
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`41`, `37`, [Bidirectional], `uio[4]`,
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`42`, `38`, [Bidirectional], `uio[5]`,
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`43`, `39`, [Bidirectional], `uio[6]`,
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`44`, `40`, [Bidirectional], `uio[7]`,
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`45`, `EPAD`, [Ground], [GND IO],
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`46`, `41`, [Input], `ui[0]`,
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`47`, `42`, [Input], `ui[1]`,
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`48`, `43`, [Input], `ui[2]`,
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`49`, `44`, [Input], `ui[3]`,
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`50`, `45`, [Input], `ui[4]`,
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`51`, `46`, [Input], `ui[5]`,
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`52`, `47`, [Input], `ui[6]`,
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`53`, `48`, [Input], `ui[7]`,
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`54`, `49`, [Input], [`u_rst_n` $dagger$],
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`55`, `50`, [Input], [`u_clk` $dagger$],
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`56`, `EPAD`, [Ground], [GND IO],
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`57`, `51`, [Power], [VDD IO],
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`58`, `52`, [Analog], `analog[12]`,
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`59`, `53`, [Analog], `analog[13]`,
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`60`, `54`, [Analog], `analog[14]`,
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`61`, `55`, [Analog], `analog[15]`,
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`62`, `EPAD`, [Ground], [GND Analog],
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`63`, `56`, [Power], [PWR Analog],
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`64`, `57`, [Analog], `analog[16]`,
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`65`, `58`, [Analog], `analog[17]`,
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`66`, `59`, [Analog], `analog[18]`,
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`67`, `60`, [Analog], `analog[19]`,
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`68`, `61`, [Analog], `analog[20]`,
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`69`, `62`, [Analog], `analog[21]`,
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`70`, `EPAD`, [Ground], [GND Core],
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`71`, `63`, [Power], [VDD Core],
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`72`, `EPAD`, [Ground], [GND IO],
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`73`, `64`, [Power], [VDD IO]
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)
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)
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[
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$dagger$ Internally, there's no difference between `u_clk`, `u_rst_n`, and `ui` pins. They are all just bits in the
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`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
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]
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}
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@@ -1,11 +0,0 @@
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#import "../src/lib.typ": get_image_by_id
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= Pinout
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The chip is packaged in a 64-pin QFN package. The pinout is shown below.
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#align(center, get_image_by_id("images", "chip_pinout_qfn64"))
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Note: You will receive the chip mounted on a breakout board
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(#link("https://github.com/tinytapeout/breakout-pcb")[github.com/tinytapeout/breakout-pcb]).
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The pinout is provided for advanced users, as most users will not need to solder the chip directly.
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