diff --git a/configure.py b/configure.py index 5c72256..e49fc26 100755 --- a/configure.py +++ b/configure.py @@ -82,7 +82,7 @@ class Projects: project.golden_harden() if args.update_shuttle: - project.check_ports(True) + project.check_ports(bool(config.get("powered_netlists", True))) project.check_num_cells() self.projects.append(project) diff --git a/shuttle.py b/shuttle.py index 713c340..5c6afce 100644 --- a/shuttle.py +++ b/shuttle.py @@ -32,6 +32,7 @@ class ShuttleConfig: self.modules_yaml_name = modules_yaml_name self.mux_config_yaml_name = os.environ.get("TT_CONFIG", "sky130.yaml") self.tt_top_macro = config.get("top_level_macro", "openframe_project_wrapper") + self.netlist_type = "pnl" if self.config.get("powered_netlists", True) else "nl" self.read_mux_config_file() total_rows: int = self.mux_config["tt"]["grid"]["y"] @@ -186,6 +187,7 @@ class ShuttleConfig: copy_print_glob("projects/*/*.gds", "tt-multiplexer/ol2/tt_top/gds") copy_print_glob("projects/*/*.lef", "tt-multiplexer/ol2/tt_top/lef") copy_print_glob("projects/*/*.v", "tt-multiplexer/ol2/tt_top/verilog") + netlist_type = self.netlist_type macros = ["tt_um_chip_rom", "tt_ctrl", "tt_mux"] for macro in macros: lastrun = self.find_last_run(macro) @@ -198,7 +200,7 @@ class ShuttleConfig: f"tt-multiplexer/ol2/tt_top/lef/{macro}.lef", ) copy_print( - f"{lastrun}/final/pnl/{macro}.pnl.v", + f"{lastrun}/final/{netlist_type}/{macro}.{netlist_type}.v", f"tt-multiplexer/ol2/tt_top/verilog/{macro}.v", ) copy_print_glob( @@ -255,12 +257,13 @@ class ShuttleConfig: def create_efabless_submission(self): logging.info("creating efabless submission directory:") + netlist_type = self.netlist_type lastrun = self.find_last_run("tt_top") copy_print("shuttle_index.md", "efabless/README.md") copy_print("shuttle_index.json", "efabless/shuttle_index.json") copy_print("verilog/rtl/user_defines.v", "efabless/verilog/rtl/user_defines.v") copy_print( - f"{lastrun}/final/pnl/{self.tt_top_macro}.pnl.v", + f"{lastrun}/final/{netlist_type}/{self.tt_top_macro}.{netlist_type}.v", f"efabless/verilog/gl/{self.tt_top_macro}.v", ) copy_print(