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fix(precheck): use non-greedy regex for stripping verilog comments

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as suggested by @smunaut
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htfab
2025-09-01 23:26:45 +02:00
parent e323cb5c24
commit 5c12dd81f3
1 changed files with 1 additions and 1 deletions
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precheck/precheck.py
+1 -1
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@@ -161,7 +161,7 @@ def power_pin_check(verilog: str, lef: str, uses_3v3: bool):
# naive but good enough way to ignore comments
verilog_s = re.sub("//.*", "", verilog_s)
verilog_s = re.sub("/\\*.*\\*/", "", verilog_s, flags=(re.DOTALL | re.MULTILINE))
verilog_s = re.sub("/\\*.*?\\*/", "", verilog_s, flags=(re.DOTALL | re.MULTILINE))
for ft, s in (("Verilog", verilog_s), ("LEF", lef_s)):
for pwr, ex in (("VGND", True), ("VDPWR", True), ("VAPWR", uses_3v3)):