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feat: sram support

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This commit is contained in:
Uri Shaked
2023-06-01 21:26:06 +03:00
parent 44f7e48fc3
commit 63645d47c9
2 changed files with 17 additions and 4 deletions
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caravel.py
+11 -2
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@@ -12,13 +12,16 @@ class CaravelConfig():
self.script_dir = os.path.dirname(os.path.realpath(__file__))
# update caravel config
def create_macro_config(self):
def create_macro_config(self, extra_macros=[]):
with open(os.path.join(self.script_dir, 'caravel_template', 'upw_config.json')) as fh:
caravel_config = json.load(fh)
logging.info("GDS and LEF")
lef_prefix = "dir::../../lef/"
gds_prefix = "dir::../../gds/"
for macro_name in extra_macros:
caravel_config["EXTRA_LEFS"].append(f"{lef_prefix}{macro_name}.lef")
caravel_config["EXTRA_GDS_FILES"].append(f"{gds_prefix}{macro_name}.gds")
for project in self.projects:
if not project.is_fill():
caravel_config["EXTRA_LEFS"].append(lef_prefix + project.get_macro_lef_filename())
@@ -28,9 +31,11 @@ class CaravelConfig():
json.dump(caravel_config, fh, indent=4)
# instantiate inside user_project_wrapper
def instantiate(self):
def instantiate(self, extra_macros=[]):
# build the blackbox_project_includes.v file - used for blackboxing when building the GDS
with open('verilog/blackbox_project_includes.v', 'w') as fh:
for macro_name in extra_macros:
fh.write(f'`include "rtl/{macro_name}.v"\n')
for project in self.projects:
if not project.is_fill():
fh.write(f'`include "gl/{project.get_gl_verilog_filename()}"\n')
@@ -51,6 +56,8 @@ class CaravelConfig():
fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_tbuf.v\n')
fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_zbuf.v\n')
fh.write('-v $(USER_PROJECT_VERILOG)/rtl/cells.v\n')
for macro_name in extra_macros:
fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{macro_name}.v\n')
for project in self.projects:
if not project.is_fill():
fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{project.get_top_verilog_filename()}\n')
@@ -60,6 +67,8 @@ class CaravelConfig():
fh.write('-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v\n')
fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_ctrl.v\n')
fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_mux.v\n')
for macro_name in extra_macros:
fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{macro_name}.v\n')
for project in self.projects:
if not project.is_fill():
fh.write(f'-v $(USER_PROJECT_VERILOG)/gl/{project.get_gl_verilog_filename()}\n')