From 1ab2abc8d5f24d04401b247f060f82411be9eab5 Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Tue, 16 Sep 2025 18:49:18 +0300 Subject: [PATCH 1/4] feat: initial gf180mcuD support --- tech.py | 43 +++- tech/gf180mcuD/def/tt_block_1x1_pgvdd.def | 232 ++++++++++++++++++++++ tech/gf180mcuD/def/tt_block_1x2_pgvdd.def | 232 ++++++++++++++++++++++ tech/gf180mcuD/def/tt_block_2x2_pgvdd.def | 232 ++++++++++++++++++++++ tech/gf180mcuD/def/tt_block_3x2_pgvdd.def | 232 ++++++++++++++++++++++ tech/gf180mcuD/def/tt_block_3x4_pgvdd.def | 232 ++++++++++++++++++++++ tech/gf180mcuD/def/tt_block_4x2_pgvdd.def | 232 ++++++++++++++++++++++ tech/gf180mcuD/def/tt_block_4x4_pgvdd.def | 232 ++++++++++++++++++++++ tech/gf180mcuD/tile_sizes.yaml | 7 + tt_tool.py | 9 +- 10 files changed, 1680 insertions(+), 3 deletions(-) create mode 100644 tech/gf180mcuD/def/tt_block_1x1_pgvdd.def create mode 100644 tech/gf180mcuD/def/tt_block_1x2_pgvdd.def create mode 100644 tech/gf180mcuD/def/tt_block_2x2_pgvdd.def create mode 100644 tech/gf180mcuD/def/tt_block_3x2_pgvdd.def create mode 100644 tech/gf180mcuD/def/tt_block_3x4_pgvdd.def create mode 100644 tech/gf180mcuD/def/tt_block_4x2_pgvdd.def create mode 100644 tech/gf180mcuD/def/tt_block_4x4_pgvdd.def create mode 100644 tech/gf180mcuD/tile_sizes.yaml diff --git a/tech.py b/tech.py index 95898a9..a6698f8 100644 --- a/tech.py +++ b/tech.py @@ -4,7 +4,7 @@ from typing import Dict, List, Literal, Protocol, Tuple, TypedDict from git.repo import Repo -TechName = Literal["sky130A", "ihp-sg13g2"] +TechName = Literal["sky130A", "ihp-sg13g2", "gf180mcuD"] class CellDefinition(TypedDict): @@ -150,7 +150,46 @@ class IHPTech(Tech): return cells +class GF180MCUDTech(Tech): + def_suffix = "pgvdd" + librelane_pdk_args = "--pdk gf180mcuD" + tt_corner = "nom_tt_025C_5v00" + cell_regexp = r"gf180mcu_(?P\S+)__(?P\S+)_(?P\d+)" + netlist_type = "pnl" + project_top_metal_layer = "Metal4" + label_layers = [ + # TODO: add label layers + ] + buried_layers = [ + # TODO: add buried layers + ] + mux_config_yaml_name = "gf180mcuD.yaml" + mux_macros = [ + "pg/gf180mcuD/tt_pg_1v8_hp_1", + "pg/gf180mcuD/tt_pg_1v8_hp_2", + "pg/gf180mcuD/tt_pg_1v8_hp_4", + "pg/gf180mcuD/tt_pg_1v8_ll_1", + "pg/gf180mcuD/tt_pg_1v8_ll_2", + "pg/gf180mcuD/tt_pg_1v8_ll_4", + ] + extra_logo_macros = [] + + def read_pdk_version(self, pdk_root: str) -> PDKVersionInfo: + pdk_sources_file = os.path.join(pdk_root, "gf180mcuD", "SOURCES") + return parse_openpdks_pdk_version(pdk_sources_file) + + def load_cell_definitions(self) -> Dict[str, CellDefinition]: + URL_FORMAT = "https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/cells/{name}/README.html" + script_dir = os.path.dirname(os.path.realpath(__file__)) + with open(os.path.join(script_dir, "tech/sky130A/cells.json")) as fh: + cells = json.load(fh) + for name, cell in cells.items(): + cell["url"] = URL_FORMAT.format(name=name) + return cells + + tech_map: dict[TechName, Tech] = { - "sky130A": Sky130Tech(), "ihp-sg13g2": IHPTech(), + "gf180mcuD": GF180MCUDTech(), + "sky130A": Sky130Tech(), } diff --git a/tech/gf180mcuD/def/tt_block_1x1_pgvdd.def b/tech/gf180mcuD/def/tt_block_1x1_pgvdd.def new file mode 100644 index 0000000..ba869cc --- /dev/null +++ b/tech/gf180mcuD/def/tt_block_1x1_pgvdd.def @@ -0,0 +1,232 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 693280 321440 ) ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626080 320440 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 640640 320440 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 611520 320440 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 596960 320440 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582400 320440 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 567840 320440 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553280 320440 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 538720 320440 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524160 320440 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 509600 320440 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495040 320440 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 480480 320440 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 465920 320440 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451360 320440 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 436800 320440 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422240 320440 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 407680 320440 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393120 320440 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 378560 320440 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131040 320440 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 116480 320440 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 101920 320440 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87360 320440 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 72800 320440 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58240 320440 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 43680 320440 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29120 320440 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 247520 320440 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 232960 320440 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218400 320440 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 203840 320440 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189280 320440 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 174720 320440 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160160 320440 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 145600 320440 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364000 320440 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 349440 320440 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 334880 320440 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320320 320440 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 305760 320440 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291200 320440 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 276640 320440 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262080 320440 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD + USE POWER ; + - VSS + USE GROUND ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/tt_block_1x2_pgvdd.def b/tech/gf180mcuD/def/tt_block_1x2_pgvdd.def new file mode 100644 index 0000000..f26b93b --- /dev/null +++ b/tech/gf180mcuD/def/tt_block_1x2_pgvdd.def @@ -0,0 +1,232 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 693280 650720 ) ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626080 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 640640 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 611520 649720 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 596960 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582400 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 567840 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553280 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 538720 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524160 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 509600 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495040 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 480480 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 465920 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451360 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 436800 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422240 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 407680 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393120 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 378560 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131040 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 116480 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 101920 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87360 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 72800 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58240 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 43680 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29120 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 247520 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 232960 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218400 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 203840 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189280 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 174720 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160160 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 145600 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364000 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 349440 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 334880 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320320 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 305760 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291200 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 276640 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262080 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD + USE POWER ; + - VSS + USE GROUND ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/tt_block_2x2_pgvdd.def b/tech/gf180mcuD/def/tt_block_2x2_pgvdd.def new file mode 100644 index 0000000..91bb9fb --- /dev/null +++ b/tech/gf180mcuD/def/tt_block_2x2_pgvdd.def @@ -0,0 +1,232 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 1422400 650720 ) ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626080 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 640640 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 611520 649720 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 596960 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582400 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 567840 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553280 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 538720 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524160 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 509600 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495040 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 480480 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 465920 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451360 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 436800 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422240 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 407680 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393120 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 378560 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131040 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 116480 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 101920 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87360 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 72800 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58240 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 43680 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29120 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 247520 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 232960 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218400 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 203840 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189280 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 174720 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160160 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 145600 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364000 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 349440 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 334880 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320320 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 305760 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291200 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 276640 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262080 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD + USE POWER ; + - VSS + USE GROUND ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/tt_block_3x2_pgvdd.def b/tech/gf180mcuD/def/tt_block_3x2_pgvdd.def new file mode 100644 index 0000000..103331c --- /dev/null +++ b/tech/gf180mcuD/def/tt_block_3x2_pgvdd.def @@ -0,0 +1,232 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 2151520 650720 ) ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626080 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 640640 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 611520 649720 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 596960 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582400 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 567840 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553280 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 538720 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524160 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 509600 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495040 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 480480 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 465920 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451360 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 436800 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422240 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 407680 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393120 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 378560 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131040 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 116480 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 101920 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87360 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 72800 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58240 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 43680 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29120 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 247520 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 232960 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218400 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 203840 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189280 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 174720 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160160 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 145600 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364000 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 349440 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 334880 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320320 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 305760 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291200 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 276640 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262080 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD + USE POWER ; + - VSS + USE GROUND ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/tt_block_3x4_pgvdd.def b/tech/gf180mcuD/def/tt_block_3x4_pgvdd.def new file mode 100644 index 0000000..b607736 --- /dev/null +++ b/tech/gf180mcuD/def/tt_block_3x4_pgvdd.def @@ -0,0 +1,232 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 2151520 1473920 ) ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626080 1472920 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 640640 1472920 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 611520 1472920 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 596960 1472920 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582400 1472920 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 567840 1472920 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553280 1472920 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 538720 1472920 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524160 1472920 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 509600 1472920 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495040 1472920 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 480480 1472920 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 465920 1472920 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451360 1472920 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 436800 1472920 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422240 1472920 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 407680 1472920 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393120 1472920 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 378560 1472920 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131040 1472920 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 116480 1472920 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 101920 1472920 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87360 1472920 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 72800 1472920 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58240 1472920 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 43680 1472920 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29120 1472920 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 247520 1472920 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 232960 1472920 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218400 1472920 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 203840 1472920 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189280 1472920 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 174720 1472920 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160160 1472920 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 145600 1472920 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364000 1472920 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 349440 1472920 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 334880 1472920 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320320 1472920 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 305760 1472920 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291200 1472920 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 276640 1472920 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262080 1472920 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD + USE POWER ; + - VSS + USE GROUND ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/tt_block_4x2_pgvdd.def b/tech/gf180mcuD/def/tt_block_4x2_pgvdd.def new file mode 100644 index 0000000..a2a5b27 --- /dev/null +++ b/tech/gf180mcuD/def/tt_block_4x2_pgvdd.def @@ -0,0 +1,232 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 2880640 650720 ) ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626080 649720 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 640640 649720 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 611520 649720 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 596960 649720 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582400 649720 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 567840 649720 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553280 649720 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 538720 649720 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524160 649720 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 509600 649720 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495040 649720 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 480480 649720 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 465920 649720 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451360 649720 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 436800 649720 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422240 649720 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 407680 649720 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393120 649720 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 378560 649720 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131040 649720 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 116480 649720 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 101920 649720 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87360 649720 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 72800 649720 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58240 649720 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 43680 649720 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29120 649720 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 247520 649720 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 232960 649720 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218400 649720 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 203840 649720 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189280 649720 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 174720 649720 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160160 649720 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 145600 649720 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364000 649720 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 349440 649720 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 334880 649720 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320320 649720 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 305760 649720 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291200 649720 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 276640 649720 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262080 649720 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD + USE POWER ; + - VSS + USE GROUND ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/def/tt_block_4x4_pgvdd.def b/tech/gf180mcuD/def/tt_block_4x4_pgvdd.def new file mode 100644 index 0000000..c78fe15 --- /dev/null +++ b/tech/gf180mcuD/def/tt_block_4x4_pgvdd.def @@ -0,0 +1,232 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 2880640 1473920 ) ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 626080 1472920 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 640640 1472920 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 611520 1472920 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 596960 1472920 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 582400 1472920 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 567840 1472920 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 553280 1472920 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 538720 1472920 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 524160 1472920 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 509600 1472920 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 495040 1472920 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 480480 1472920 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 465920 1472920 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 451360 1472920 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 436800 1472920 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 422240 1472920 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 407680 1472920 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 393120 1472920 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 378560 1472920 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 131040 1472920 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 116480 1472920 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 101920 1472920 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 87360 1472920 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 72800 1472920 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 58240 1472920 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 43680 1472920 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 29120 1472920 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 247520 1472920 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 232960 1472920 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 218400 1472920 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 203840 1472920 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 189280 1472920 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 174720 1472920 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 160160 1472920 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 145600 1472920 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 364000 1472920 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 349440 1472920 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 334880 1472920 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 320320 1472920 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 305760 1472920 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 291200 1472920 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 276640 1472920 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal4 ( -300 -1000 ) ( 300 1000 ) + + PLACED ( 262080 1472920 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD + USE POWER ; + - VSS + USE GROUND ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/tech/gf180mcuD/tile_sizes.yaml b/tech/gf180mcuD/tile_sizes.yaml new file mode 100644 index 0000000..fbd7f59 --- /dev/null +++ b/tech/gf180mcuD/tile_sizes.yaml @@ -0,0 +1,7 @@ +1x1: "0 0 346.64 160.72" +1x2: "0 0 346.64 325.36" +2x2: "0 0 711.20 325.36" +3x2: "0 0 1075.76 325.36" +3x4: "0 0 1075.76 736.96" +4x2: "0 0 1440.32 325.36" +4x4: "0 0 1440.32 736.96" diff --git a/tt_tool.py b/tt_tool.py index 0c35763..19490f2 100755 --- a/tt_tool.py +++ b/tt_tool.py @@ -27,6 +27,13 @@ if __name__ == "__main__": const=True, default=False, ) + parser.add_argument( + "--gf", + help="use gf180mcuD PDK", + action="store_const", + const=True, + default=False, + ) # reports & summaries parser.add_argument( @@ -147,7 +154,7 @@ if __name__ == "__main__": ch.setFormatter(log_format) log.addHandler(ch) - pdk: TechName = "ihp-sg13g2" if args.ihp else "sky130A" + pdk: TechName = "ihp-sg13g2" if args.ihp else "gf180mcuD" if args.gf else "sky130A" project = Project(0, "unknown", args.project_dir, pdk, is_user_project=True) project.post_clone_setup() From fcf7e8a37f4224658b6c773f5281b58a25e88d0f Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Wed, 17 Sep 2025 11:56:14 +0300 Subject: [PATCH 2/4] fix(tt_tool): always specify the power pin names Up to this point, we relied on the PDK's default power pin names. However, the defaults names for GF180, VDD and VSS, are not compatible with Tiny Tapeout, which expects VPWR (or VDPWR) and VGND. So instead, we set the VDD_PIN and GND_PIN config options explicitly. --- project.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/project.py b/project.py index 683ff61..6859686 100644 --- a/project.py +++ b/project.py @@ -488,6 +488,8 @@ class Project: "VERILOG_FILES": [f"dir::{src}" for src in self.sources], "DIE_AREA": die_area, "FP_DEF_TEMPLATE": def_template, + "VDD_PIN": "VPWR", + "GND_PIN": "VGND", "RT_MAX_LAYER": self.tech.project_top_metal_layer, } write_config(config, os.path.join(self.src_dir, "user_config"), ("json",)) From 0afaaef4d47209798607fe0291d676006f72d1e6 Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Wed, 17 Sep 2025 13:37:56 +0300 Subject: [PATCH 3/4] ci(test-harden): add gf180mcuD --- .github/workflows/test-harden.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/.github/workflows/test-harden.yaml b/.github/workflows/test-harden.yaml index 3aecc0a..1698c4f 100644 --- a/.github/workflows/test-harden.yaml +++ b/.github/workflows/test-harden.yaml @@ -10,7 +10,7 @@ jobs: strategy: fail-fast: false matrix: - pdk: [sky130A, ihp-sg13g2] + pdk: [sky130A, ihp-sg13g2, gf180mcuD] runs-on: ubuntu-24.04 @@ -43,8 +43,8 @@ jobs: if: "${{ matrix.pdk == 'ihp-sg13g2' }}" run: pip install librelane==${LIBRELANE_VERSION_DEV} - - name: Clone the factory test (sky130A) - if: "${{ matrix.pdk == 'sky130A' }}" + - name: Clone the factory test + if: "${{ matrix.pdk != 'ihp-sg13g2' }}" run: git clone https://github.com/tinytapeout/ttsky25a-factory-test ${PROJECT_DIR} - name: Clone the factory test (ihp-sg13g2) @@ -55,10 +55,14 @@ jobs: if: "${{ matrix.pdk == 'ihp-sg13g2' }}" run: git clone -b tt2025 --depth 1 https://github.com/TinyTapeout/IHP-Open-PDK ${PDK_ROOT} - - name: Configure tt_tool.py args + - name: Configure tt_tool.py args (IHP) if: "${{ matrix.pdk == 'ihp-sg13g2' }}" run: echo "TT_TOOL_ARGS=--ihp" >> $GITHUB_ENV + - name: Configure tt_tool.py args (gf180mcuD) + if: "${{ matrix.pdk == 'gf180mcuD' }}" + run: echo "TT_TOOL_ARGS=--gf" >> $GITHUB_ENV + - name: Copy tt-support-tools to the project directory run: cp -r . ${PROJECT_DIR}/tt @@ -77,6 +81,7 @@ jobs: - name: Print stats working-directory: ${{ env.PROJECT_DIR }} run: | + set -e python ./tt/tt_tool.py $TT_TOOL_ARGS --print-stats --print-warnings --print-cell-summary --print-cell-category | tee $GITHUB_STEP_SUMMARY - name: Create SVG render From 1b336f49963f3157f86b11272a1b42297647daab Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Sun, 28 Sep 2025 16:04:43 +0300 Subject: [PATCH 4/4] feat(tt_tool): cell/category definitions for gf180mcuD Enables the --print-cell-summary and --print-cell-category commands for gf projects --- project.py | 2 - tech.py | 7 +- tech/gf180mcuD/categories.json | 91 + tech/gf180mcuD/cells.json | 3510 ++++++++++++++++++++++++++ tech/gf180mcuD/gf180mcu_cell_defs.py | 49 + 5 files changed, 3654 insertions(+), 5 deletions(-) create mode 100644 tech/gf180mcuD/categories.json create mode 100644 tech/gf180mcuD/cells.json create mode 100644 tech/gf180mcuD/gf180mcu_cell_defs.py diff --git a/project.py b/project.py index 6859686..616560b 100644 --- a/project.py +++ b/project.py @@ -994,9 +994,7 @@ class Project: if m is not None: total += 1 gd = m.groupdict() - cell_lib = gd.get("cell_lib", "") cell_name = gd["cell_name"] - assert cell_lib in ["fd_sc_hd", "ef_sc_hd", ""] try: cell_count[cell_name] += 1 except KeyError: diff --git a/tech.py b/tech.py index a6698f8..7d781a8 100644 --- a/tech.py +++ b/tech.py @@ -179,12 +179,13 @@ class GF180MCUDTech(Tech): return parse_openpdks_pdk_version(pdk_sources_file) def load_cell_definitions(self) -> Dict[str, CellDefinition]: - URL_FORMAT = "https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/cells/{name}/README.html" + URL_FORMAT = "https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/gf180mcu_fd_sc_mcu7t5v0/cells/{name}/gf180mcu_fd_sc_mcu7t5v0__{name}{variant}.html" script_dir = os.path.dirname(os.path.realpath(__file__)) - with open(os.path.join(script_dir, "tech/sky130A/cells.json")) as fh: + with open(os.path.join(script_dir, "tech/gf180mcuD/cells.json")) as fh: cells = json.load(fh) for name, cell in cells.items(): - cell["url"] = URL_FORMAT.format(name=name) + variant = cell["variants"][0] if cell["variants"] else "" + cell["url"] = URL_FORMAT.format(name=name, variant=variant) return cells diff --git a/tech/gf180mcuD/categories.json b/tech/gf180mcuD/categories.json new file mode 100644 index 0000000..1441540 --- /dev/null +++ b/tech/gf180mcuD/categories.json @@ -0,0 +1,91 @@ +{ + "categories": [ + "AND", + "OR", + "NAND", + "NOR", + "Clock", + "Flip Flops", + "Multiplexer", + "Latch", + "Inverter", + "Buffer", + "Fill", + "Tap", + "Diode", + "Combo Logic", + "Misc", + "Adder" + ], + "map": { + "addf": 15, + "addh": 15, + "and2": 0, + "and3": 0, + "and4": 0, + "antenna": 12, + "aoi21": 13, + "aoi211": 13, + "aoi22": 13, + "aoi221": 13, + "aoi222": 13, + "buf": 9, + "bufz": 14, + "clkbuf": 9, + "clkinv": 4, + "dffnq": 5, + "dffnrnq": 5, + "dffnrsnq": 5, + "dffnsnq": 5, + "dffq": 5, + "dffrnq": 5, + "dffrsnq": 5, + "dffsnq": 5, + "dlya": 9, + "dlyb": 9, + "dlyc": 9, + "dlyd": 9, + "endcap": 14, + "fill": 10, + "fillcap": 10, + "filltie": 10, + "hold": 14, + "icgtn": 4, + "icgtp": 4, + "inv": 8, + "invz": 8, + "latq": 7, + "latrnq": 7, + "latrsnq": 7, + "latsnq": 7, + "mux2": 6, + "mux4": 6, + "nand2": 2, + "nand3": 2, + "nand4": 2, + "nor2": 3, + "nor3": 3, + "nor4": 3, + "oai21": 13, + "oai211": 13, + "oai22": 13, + "oai221": 13, + "oai222": 13, + "oai31": 13, + "oai32": 13, + "oai33": 13, + "or2": 1, + "or3": 1, + "or4": 1, + "sdffq": 5, + "sdffrnq": 5, + "sdffrsnq": 5, + "sdffsnq": 5, + "tieh": 14, + "tiel": 14, + "xnor2": 3, + "xnor3": 3, + "xor2": 1, + "xor3": 1 + } +} diff --git a/tech/gf180mcuD/cells.json b/tech/gf180mcuD/cells.json new file mode 100644 index 0000000..f5a56fb --- /dev/null +++ b/tech/gf180mcuD/cells.json @@ -0,0 +1,3510 @@ +{ + "aoi22": { + "description": "two 2-input AND into 2-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi22", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "aoi22", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "B1", + "input", + "" + ], + [ + "signal", + "B2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__aoi22", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "addf": { + "description": "Full Adder", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__addf", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "addf", + "parameters": [], + "ports": [ + [ + "signal", + "A", + "input", + "" + ], + [ + "signal", + "B", + "input", + "" + ], + [ + "signal", + "CI", + "input", + "" + ], + [ + "signal", + "CO", + "output", + "" + ], + [ + "signal", + "S", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__addf", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "xnor3": { + "description": "3-input exclusive NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xnor3", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "xnor3", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xnor3", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "and3": { + "description": "3-input AND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and3", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "and3", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and3", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "and2": { + "description": "2-input AND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "and2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and2", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "or2": { + "description": "2-input OR(A1", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__or2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "or2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__or2", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "xnor2": { + "description": "2-input exclusive NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__xnor2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "xnor2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__xnor2", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "sdffrnq": { + "description": "positive edge triggered scan D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffrnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "sdffrnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "SE", + "input", + "" + ], + [ + "signal", + "SI", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffrnq", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "and4": { + "description": "4-input AND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__and4", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "and4", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "A3", + "input", + "" + ], + [ + "signal", + "A4", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__and4", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "sdffsnq": { + "description": "positive edge triggered scan D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "sdffsnq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "SE", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "SI", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffsnq", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "latrnq": { + "description": "positive D-latch", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latrnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "latrnq", + "parameters": [], + "ports": [ + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "E", + "input", + "" + ], + [ + "signal", + "RN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latrnq", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "nand2": { + "description": "2-input NAND", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__nand2", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "nand2", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + "A2", + "input", + "" + ], + [ + "signal", + "ZN", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__nand2", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "sdffq": { + "description": "positive edge triggered scan D-type flip flop", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__sdffq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "sdffq", + "parameters": [], + "ports": [ + [ + "signal", + "CLK", + "input", + "" + ], + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "SE", + "input", + "" + ], + [ + "signal", + "SI", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__sdffq", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "latsnq": { + "description": "positive D-latch", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__latsnq", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "latsnq", + "parameters": [], + "ports": [ + [ + "signal", + "D", + "input", + "" + ], + [ + "signal", + "E", + "input", + "" + ], + [ + "signal", + "SETN", + "input", + "" + ], + [ + "signal", + "Q", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__latsnq", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "aoi21": { + "description": "2-input AND into 2-input NOR", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__aoi21", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "aoi21", + "parameters": [], + "ports": [ + [ + "signal", + "A1", + "input", + "" + ], + [ + "signal", + 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"gf180mcu_fd_sc_mcu7t5v0__latrsnq", + "variants": [ + "_1", + "_2", + "_4" + ] + }, + "dlyb": { + "description": "4 buffer delay cell", + "file_prefix": "gf180mcu_fd_sc_mcu7t5v0__dlyb", + "library": "gf180mcu_fd_sc_mcu7t5v0", + "name": "dlyb", + "parameters": [], + "ports": [ + [ + "signal", + "I", + "input", + "" + ], + [ + "signal", + "Z", + "output", + "" + ], + [ + "power", + "VDD", + "input", + "supply1" + ], + [ + "power", + "VSS", + "input", + "supply0" + ] + ], + "type": "cell", + "verilog_name": "gf180mcu_fd_sc_mcu7t5v0__dlyb", + "variants": [ + "_1", + "_2", + "_4" + ] + } +} \ No newline at end of file diff --git a/tech/gf180mcuD/gf180mcu_cell_defs.py b/tech/gf180mcuD/gf180mcu_cell_defs.py new file mode 100644 index 0000000..b867602 --- /dev/null +++ b/tech/gf180mcuD/gf180mcu_cell_defs.py @@ -0,0 +1,49 @@ +# Create a JSON file with cell definitions from the gf180mcu_fd_sc_mcu7t5v0 standard cell library. +# To run this script, first clone the standard cell library by running: +# +# git clone --depth 1 https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 gf180mcu_fd_sc_mcu7t5v0 + +import glob +import json +import os +from typing import Dict, List, TypedDict + + +class GF180Cell(TypedDict): + description: str + file_prefix: str + library: str + name: str + parameters: List[str] + ports: List[List[str]] # kind, name, direction, description + type: str + verilog_name: str + """ + Each variant is a different drive strength (e.g. _1, _2, _4, etc.). + Cells with a single drive strength have the empty string as variant. + """ + variants: List[str] + + +def create_cell_defs(): + json_files = glob.glob("gf180mcu_fd_sc_mcu7t5v0/cells/*/definition.json") + definitions: Dict[str, GF180Cell] = {} + for json_file in json_files: + with open(json_file) as fh: + definition: GF180Cell = json.load(fh) + definitions[definition["name"]] = definition + variants = [] + for item in os.listdir(os.path.dirname(json_file)): + if item.startswith(definition["file_prefix"]) and item.endswith(".gds"): + variants.append(item[len(definition["file_prefix"]) : -4]) + variants.sort() + definition["variants"] = variants + print(definition["name"], variants) + + script_dir = os.path.dirname(os.path.realpath(__file__)) + with open(f"{script_dir}/cells.json", "w") as fh: + json.dump(definitions, fh, indent=2) + + +if __name__ == "__main__": + create_cell_defs()