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fix(precheck): power pins should be on met2 for micro tiles

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This commit is contained in:
Uri Shaked
2024-09-05 13:43:28 +03:00
parent 894bc331f1
commit 6f5c5de2b2
1 changed files with 5 additions and 2 deletions
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precheck/pin_check.py
+5 -2
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@@ -183,6 +183,9 @@ def pin_check(gds: str, lef: str, template_def: str, toplevel: str, uses_3v3: bo
if uses_3v3: if uses_3v3:
power_pins.append("VAPWR") power_pins.append("VAPWR")
compat_pins = {"VPWR": "VDPWR"} compat_pins = {"VPWR": "VDPWR"}
power_pins_layer = "met4"
if "tt_block_micro" in template_def:
power_pins_layer = "met2"
macro_active = False macro_active = False
pins_expected = set(def_pins).union(power_pins).union(compat_pins) pins_expected = set(def_pins).union(power_pins).union(compat_pins)
@@ -307,9 +310,9 @@ def pin_check(gds: str, lef: str, template_def: str, toplevel: str, uses_3v3: bo
else: else:
for layer, lx, by, rx, ty in lef_ports[current_pin]: for layer, lx, by, rx, ty in lef_ports[current_pin]:
width = rx - lx width = rx - lx
if layer != "met4": if layer != power_pins_layer:
logging.error( logging.error(
f"Port {current_pin} has wrong layer in {lef}: {layer} != met4" f"Port {current_pin} has wrong layer in {lef}: {layer} != {power_pins_layer}"
) )
lef_errors += 1 lef_errors += 1
if width < 1200: if width < 1200: