From 7b6d93c0860f9c9b304501edc458fcb1c5abf198 Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Sat, 3 Jun 2023 14:58:17 +0300 Subject: [PATCH] feat: support for openlane2 mux verification --- caravel.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/caravel.py b/caravel.py index 3ba710e..6467678 100644 --- a/caravel.py +++ b/caravel.py @@ -61,6 +61,27 @@ class CaravelConfig(): for project in self.projects: if not project.is_fill(): fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{project.get_top_verilog_filename()}\n') + with open('verilog/includes/includes.rtl.caravel_user_project.openlane2', 'w') as fh: + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/ol2/tt_top/user_project_wrapper.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_top.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_ctrl.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_mux.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_user_module.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_buf.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_dfrbp.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_diode.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_inv.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_mux4.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tbuf_pol.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tbuf.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tie.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_zbuf.v\n') + fh.write('-v $(USER_PROJECT_VERILOG)/rtl/cells.v\n') + for macro_name in extra_macros: + fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{macro_name}.v\n') + for project in self.projects: + if not project.is_fill(): + fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{project.get_top_verilog_filename()}\n') # build GL includes with open('verilog/includes/includes.gl.caravel_user_project', 'w') as fh: