mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 12:46:08 +01:00
Update submission tools for mux
1. don't generate user_project_wrapper.v, as it's now static 2. don't generate macros.cfg, as gen_macro_cfg.py does it (eventually, we'll want to integrate it into tt-support-tools) 3. don't generate PDN hooks config. Instead, we're using a wildcard to match all user macros. 4. remove the "layout" section from config.yaml, and scanchain related stuff from generate config.json
This commit is contained in:
Uri Shaked
+1
-191
@@ -11,97 +11,14 @@ class CaravelConfig():
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self.num_projects = num_projects
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self.script_dir = os.path.dirname(os.path.realpath(__file__))
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# co-ords are bottom left corner
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def place_macro(self, x, y, instance, rotate, fh):
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c = self.config['layout']
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if not rotate:
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# scanchain first
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orientation = 'N'
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macro_instance = self.projects[instance].get_scanchain_instance()
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fh.write(f"{macro_instance} {x:<4} {y:<4} {orientation}\n")
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macro_instance = self.projects[instance].get_macro_instance()
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x = x + c['scanchain_w'] + c['scanchain_spc']
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fh.write(f"{macro_instance} {x:<4} {y:<4} {orientation}\n")
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else:
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# macro first
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orientation = 'S'
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macro_instance = self.projects[instance].get_macro_instance()
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fh.write(f"{macro_instance} {x:<4} {y:<4} {orientation}\n")
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macro_instance = self.projects[instance].get_scanchain_instance()
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x = x + c['module_w'] + c['scanchain_spc']
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y = y + c['module_h'] - c['scanchain_h']
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fh.write(f"{macro_instance} {x:<4} {y:<4} {orientation}\n")
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# create macro file & positions, power hooks
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# update caravel config
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def create_macro_config(self):
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# array size
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c = self.config['layout']
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pos_x = 2
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pos_y = 0
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dir_x = 1
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dir_y = 1
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# macro.cfg: where macros are placed
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logging.info("creating macro.cfg")
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with open("openlane/user_project_wrapper/macro.cfg", 'w') as fh:
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fh.write(f"scan_controller {c['scan_control_x']} {c['scan_control_y']} N\n")
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for i in range(self.num_projects):
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logging.debug(f"Block {i:d} at ({pos_x:d}, {pos_y:d})")
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# calculate 0, 0 point
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macro_x = c['start_x'] + pos_x * (c['module_w'] + c['scanchain_w'] + c['scanchain_spc'] + c['space_x'])
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macro_y = c['start_y'] + pos_y * (c['module_h'] + c['space_y'])
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# rotated?
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if dir_x == 1:
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rotate = False
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else:
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rotate = True
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self.place_macro(macro_x, macro_y, i, rotate, fh)
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# next position
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pos_x += 2 * dir_x
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if pos_x >= c['cols']:
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pos_x = c['cols'] - 1
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pos_y += dir_y
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dir_x = - dir_x
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elif pos_x < 0:
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pos_x = 0
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pos_y += dir_y
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dir_x = - dir_x
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if pos_y >= c['rows']:
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pos_y = c['rows'] - 1
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dir_y = - dir_y
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logging.info(f"total user macros placed: {self.num_projects}")
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with open(os.path.join(self.script_dir, 'caravel_template', 'upw_config.json')) as fh:
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caravel_config = json.load(fh)
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power_domains = "vccd1 vssd1 vccd1 vssd1"
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power_config = []
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logging.info("creating macro hooks")
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for i in range(self.num_projects):
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power_config.append(f"{self.projects[i].get_scanchain_instance()} {power_domains},")
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power_config.append(f"{self.projects[i].get_macro_instance()} {power_domains},")
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power_config.append(f"scan_controller {power_domains}") # no trailing comma
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caravel_config["FP_PDN_MACRO_HOOKS"] = power_config
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logging.info("GDS and LEF")
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lef_prefix = "dir::../../lef/"
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gds_prefix = "dir::../../gds/"
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caravel_config["EXTRA_LEFS"].append(lef_prefix + "scan_controller.lef")
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caravel_config["EXTRA_LEFS"].append(lef_prefix + "scanchain.lef")
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caravel_config["EXTRA_GDS_FILES"].append(gds_prefix + "scan_controller.gds")
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caravel_config["EXTRA_GDS_FILES"].append(gds_prefix + "scanchain.gds")
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for project in self.projects:
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if not project.is_fill():
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caravel_config["EXTRA_LEFS"].append(lef_prefix + project.get_macro_lef_filename())
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@@ -112,115 +29,8 @@ class CaravelConfig():
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# instantiate inside user_project_wrapper
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def instantiate(self):
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logging.info("instantiating designs in user_project_wrapper.v")
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# NOTE: The user project wrapper initially used vectored signals for clk,
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# scan, and latch signals. However, this leads to atrocious sim
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# performance, as any change within the vectored signal is
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# interpreted as a trigger condition for re-evaluating logic (at
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# least this is the case under Icarus and Verilator). Therefore
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# single bit signals are used between stages to limit the impact
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# of any wire changing.
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# Instance the scan controller
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body = [
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"",
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"wire sc_clk_out, sc_data_out, sc_latch_out, sc_scan_out;",
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"wire sc_clk_in, sc_data_in;",
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"",
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f"scan_controller #(.NUM_DESIGNS({self.num_projects})) scan_controller (",
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" .clk (wb_clk_i),",
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" .reset (wb_rst_i),",
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" .active_select (io_in[20:12]),",
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" .inputs (io_in[28:21]),",
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" .outputs (io_out[36:29]),",
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" .ready (io_out[37]),",
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" .slow_clk (io_out[10]),",
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" .set_clk_div (io_in[11]),",
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"",
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" .scan_clk_out (sc_clk_out),",
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" .scan_clk_in (sc_clk_in),",
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" .scan_data_out (sc_data_out),",
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" .scan_data_in (sc_data_in),",
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" .scan_select (sc_scan_out),",
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" .scan_latch_en (sc_latch_out),",
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"",
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" .la_scan_clk_in (la_data_in[0]),",
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" .la_scan_data_in (la_data_in[1]),",
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" .la_scan_data_out (la_data_out[0]),",
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" .la_scan_select (la_data_in[2]),",
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" .la_scan_latch_en (la_data_in[3]),",
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"",
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" .driver_sel (io_in[9:8]),",
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"",
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" .oeb (io_oeb)",
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");",
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]
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# Instance every design on the scan chain
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for idx in range(self.num_projects):
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# First design driven by scan controller, all others are chained
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pfx = f"sw_{idx:03d}"
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prev_pfx = f"sw_{idx-1:03d}" if idx > 0 else "sc"
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# Pickup the Wokwi design ID and github URL for the project
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giturl = self.projects[idx].get_git_url()
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# Append the instance to the body
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body += [
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"",
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f"// [{idx:03d}] {giturl}",
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f"wire {pfx}_clk_out, {pfx}_data_out, {pfx}_scan_out, {pfx}_latch_out;",
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f"wire [7:0] {pfx}_module_data_in;",
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f"wire [7:0] {pfx}_module_data_out;",
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f"scanchain #(.NUM_IOS(8)) {self.projects[idx].get_scanchain_instance()} (",
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f" .clk_in ({prev_pfx}_clk_out),",
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f" .data_in ({prev_pfx}_data_out),",
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f" .scan_select_in ({prev_pfx}_scan_out),",
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f" .latch_enable_in ({prev_pfx}_latch_out),",
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f" .clk_out ({pfx}_clk_out),",
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f" .data_out ({pfx}_data_out),",
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f" .scan_select_out ({pfx}_scan_out),",
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f" .latch_enable_out({pfx}_latch_out),",
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f" .module_data_in ({pfx}_module_data_in),",
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f" .module_data_out ({pfx}_module_data_out)",
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");"
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]
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# Append the user module to the body
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body += [
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"",
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f"{self.projects[idx].get_macro_name()} {self.projects[idx].get_macro_instance()} (",
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f" .io_in ({pfx}_module_data_in),",
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f" .io_out ({pfx}_module_data_out)",
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");"
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]
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# Link the final design back to the scan controller
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body += [
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"",
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"// Connect final signals back to the scan controller",
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f"assign sc_clk_in = sw_{idx:03d}_clk_out;",
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f"assign sc_data_in = sw_{idx:03d}_data_out;",
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"",
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""
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]
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# Write to file
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with open('verilog/rtl/user_project_wrapper.v', 'w') as fh:
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# Insert the Caravel preamble
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with open(os.path.join(self.script_dir, 'caravel_template', 'upw_pre.v')) as fh_pre:
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fh.write(fh_pre.read())
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# Indent, join, and insert the module instances
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fh.write("\n".join([(" " + x).rstrip() for x in body]))
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# Insert the Caravel postamble
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with open(os.path.join(self.script_dir, 'caravel_template', 'upw_post.v')) as fh_post:
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fh.write(fh_post.read())
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# build the blackbox_project_includes.v file - used for blackboxing when building the GDS
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with open('verilog/blackbox_project_includes.v', 'w') as fh:
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fh.write('`include "rtl/scan_controller/scan_controller.v"\n')
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fh.write('`include "rtl/scanchain/scanchain.v"\n')
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for project in self.projects:
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if not project.is_fill():
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fh.write(f'`include "gl/{project.get_gl_verilog_filename()}"\n')
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