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Update submission tools for mux

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1. don't generate user_project_wrapper.v, as it's now static
2. don't generate macros.cfg, as gen_macro_cfg.py does it (eventually, we'll want to integrate it into tt-support-tools)
3. don't generate PDN hooks config. Instead, we're using a wildcard to match all user macros.
4. remove the "layout" section from config.yaml, and scanchain related stuff from generate config.json
This commit is contained in:
Uri Shaked
2023-05-24 23:48:29 +03:00
parent e5a26cde94
commit 7c557f77f9
6 changed files with 78 additions and 331 deletions
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caravel_template/upw_config.json
+63 -46
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@@ -2,23 +2,38 @@
"DESIGN_NAME": "user_project_wrapper",
"VERILOG_FILES": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/rtl/user_project_wrapper.v"
"dir::../../verilog/rtl/user_project_wrapper.v",
"dir::../../tt-multiplexer/proto/tt_top.v",
"dir::../../tt-multiplexer/proto/tt_user_module.v"
],
"VERILOG_FILES_BLACKBOX": [
"dir::../../tt-multiplexer/proto/tt_mux.v",
"dir::../../tt-multiplexer/proto/tt_ctrl.v",
"dir::../../tt-multiplexer/proto/tt_um_test.v",
"dir::../../verilog/blackbox_project_includes.v"
],
"ROUTING_CORES": 8,
"CLOCK_PERIOD": 25,
"CLOCK_PORT": "wb_clk_i",
"CLOCK_NET": "mprj.clk",
"FP_PDN_MACRO_HOOKS": [],
"FP_PDN_MACRO_HOOKS": [
"tt_top1\\.ctrl_I vccd1 vssd1 vccd1 vssd1,",
"tt_top1\\..*mux_I vccd1 vssd1 vccd1 vssd1,",
"tt_top1\\..*tt_um_I vccd1 vssd1 vccd1 vssd1"
],
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
"PDN_CFG": "dir::pdn_cfg.tcl",
"MAGIC_DEF_LABELS": 0,
"VERILOG_FILES_BLACKBOX": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/blackbox_project_includes.v"
"EXTRA_LEFS": [
"dir::../../lef/tt_ctrl.lef",
"dir::../../lef/tt_mux.lef",
"dir::../../lef/tt_um_test.lef"
],
"EXTRA_GDS_FILES": [
"dir::../../gds/tt_ctrl.gds",
"dir::../../gds/tt_mux.gds",
"dir::../../gds/tt_um_test.gds"
],
"EXTRA_LEFS": [],
"EXTRA_GDS_FILES": [],
"BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
"RUN_KLAYOUT_XOR": 0,
"RUN_KLAYOUT_DRC": 0,
"RUN_MAGIC_DRC": 0,
@@ -31,15 +46,17 @@
"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
"SYNTH_FLAT_TOP": 1,
"FP_PDN_ENABLE_RAILS": 0,
"DIODE_INSERTION_STRATEGY": 0,
"RUN_FILL_INSERTION": 0,
"RUN_TAP_DECAP_INSERTION": 0,
"FP_PDN_VPITCH": 140,
"FP_PDN_VOFFSET": 186,
"FP_PDN_HPITCH": 185,
"FP_PDN_HPITCH": 50,
"FP_PDN_HOFFSET": 160,
"CLOCK_TREE_SYNTH": 0,
"QUIT_ON_LVS_ERROR": "0",
"MAGIC_ZEROIZE_ORIGIN": 0,
"FP_SIZING": "absolute",
"RUN_CVC": 0,
@@ -62,48 +79,48 @@
"FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
"FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
"VDD_NETS": [
"vccd1",
"vccd2",
"vdda1",
"vdda2"
"vccd1",
"vccd2",
"vdda1",
"vdda2"
],
"GND_NETS": [
"vssd1",
"vssd2",
"vssa1",
"vssa2"
"vssd1",
"vssd2",
"vssa1",
"vssa2"
],
"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
"pdk::sky130*": {
"RT_MAX_LAYER": "met4",
"DIE_AREA": "0 0 2920 3520",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
"scl::sky130_fd_sc_hd": {
"CLOCK_PERIOD": 25
},
"scl::sky130_fd_sc_hdll": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
"CLOCK_PERIOD": 10,
"SYNTH_MAX_FANOUT": 5
},
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
"RT_MAX_LAYER": "met4",
"DIE_AREA": "0 0 2920 3520",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
"scl::sky130_fd_sc_hd": {
"CLOCK_PERIOD": 25
},
"scl::sky130_fd_sc_hdll": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
"CLOCK_PERIOD": 10,
"SYNTH_MAX_FANOUT": 5
},
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
},
"pdk::gf180mcuC": {
"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
"FP_PDN_CHECK_NODES": 0,
"FP_PDN_ENABLE_RAILS": 0,
"RT_MAX_LAYER": "Metal4",
"DIE_AREA": "0 0 3000 3000",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
"PL_OPENPHYSYN_OPTIMIZATIONS": 0,
"DIODE_INSERTION_STRATEGY": 0,
"MAGIC_WRITE_FULL_LEF": 0
"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
"FP_PDN_CHECK_NODES": 0,
"FP_PDN_ENABLE_RAILS": 0,
"RT_MAX_LAYER": "Metal4",
"DIE_AREA": "0 0 3000 3000",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
"PL_OPENPHYSYN_OPTIMIZATIONS": 0,
"DIODE_INSERTION_STRATEGY": 0,
"MAGIC_WRITE_FULL_LEF": 0
}
}
}
caravel_template/upw_post.v
-4
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@@ -1,4 +0,0 @@
// end of module instantiation
endmodule // user_project_wrapper
`default_nettype wire
caravel_template/upw_pre.v
-84
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@@ -1,84 +0,0 @@
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_project_wrapper
*
* This wrapper enumerates all of the pins available to the
* user for the user project.
*
* An example user project is provided in this wrapper. The
* example should be removed and replaced with the actual
* user project.
*
* THIS FILE HAS BEEN GENERATED USING multi_tools_project CODEGEN
* IF YOU NEED TO MAKE EDITS TO IT, EDIT codegen/caravel_iface_header.txt
*
*-------------------------------------------------------------
*/
module user_project_wrapper #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,
// Independent clock (on independent integer divider)
input user_clock2,
// User maskable interrupt signals
output [2:0] user_irq
);
// start of module instantiation