mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 12:46:08 +01:00
Update submission tools for mux
1. don't generate user_project_wrapper.v, as it's now static 2. don't generate macros.cfg, as gen_macro_cfg.py does it (eventually, we'll want to integrate it into tt-support-tools) 3. don't generate PDN hooks config. Instead, we're using a wildcard to match all user macros. 4. remove the "layout" section from config.yaml, and scanchain related stuff from generate config.json
This commit is contained in:
Uri Shaked
@@ -2,23 +2,38 @@
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"DESIGN_NAME": "user_project_wrapper",
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"VERILOG_FILES": [
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"dir::../../verilog/rtl/defines.v",
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"dir::../../verilog/rtl/user_project_wrapper.v"
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"dir::../../verilog/rtl/user_project_wrapper.v",
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"dir::../../tt-multiplexer/proto/tt_top.v",
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"dir::../../tt-multiplexer/proto/tt_user_module.v"
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],
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"VERILOG_FILES_BLACKBOX": [
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"dir::../../tt-multiplexer/proto/tt_mux.v",
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"dir::../../tt-multiplexer/proto/tt_ctrl.v",
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"dir::../../tt-multiplexer/proto/tt_um_test.v",
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"dir::../../verilog/blackbox_project_includes.v"
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],
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"ROUTING_CORES": 8,
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"CLOCK_PERIOD": 25,
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"CLOCK_PORT": "wb_clk_i",
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"CLOCK_NET": "mprj.clk",
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"FP_PDN_MACRO_HOOKS": [],
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"FP_PDN_MACRO_HOOKS": [
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"tt_top1\\.ctrl_I vccd1 vssd1 vccd1 vssd1,",
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"tt_top1\\..*mux_I vccd1 vssd1 vccd1 vssd1,",
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"tt_top1\\..*tt_um_I vccd1 vssd1 vccd1 vssd1"
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],
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"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
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"PDN_CFG": "dir::pdn_cfg.tcl",
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"MAGIC_DEF_LABELS": 0,
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"VERILOG_FILES_BLACKBOX": [
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"dir::../../verilog/rtl/defines.v",
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"dir::../../verilog/blackbox_project_includes.v"
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"EXTRA_LEFS": [
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"dir::../../lef/tt_ctrl.lef",
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"dir::../../lef/tt_mux.lef",
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"dir::../../lef/tt_um_test.lef"
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],
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"EXTRA_GDS_FILES": [
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"dir::../../gds/tt_ctrl.gds",
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"dir::../../gds/tt_mux.gds",
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"dir::../../gds/tt_um_test.gds"
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],
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"EXTRA_LEFS": [],
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"EXTRA_GDS_FILES": [],
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"BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
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"RUN_KLAYOUT_XOR": 0,
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"RUN_KLAYOUT_DRC": 0,
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"RUN_MAGIC_DRC": 0,
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@@ -31,15 +46,17 @@
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"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
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"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
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"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
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"SYNTH_FLAT_TOP": 1,
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"FP_PDN_ENABLE_RAILS": 0,
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"DIODE_INSERTION_STRATEGY": 0,
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"RUN_FILL_INSERTION": 0,
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"RUN_TAP_DECAP_INSERTION": 0,
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"FP_PDN_VPITCH": 140,
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"FP_PDN_VOFFSET": 186,
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"FP_PDN_HPITCH": 185,
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"FP_PDN_HPITCH": 50,
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"FP_PDN_HOFFSET": 160,
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"CLOCK_TREE_SYNTH": 0,
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"QUIT_ON_LVS_ERROR": "0",
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"MAGIC_ZEROIZE_ORIGIN": 0,
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"FP_SIZING": "absolute",
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"RUN_CVC": 0,
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@@ -62,48 +79,48 @@
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"FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
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"FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
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"VDD_NETS": [
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"vccd1",
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"vccd2",
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"vdda1",
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"vdda2"
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"vccd1",
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"vccd2",
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"vdda1",
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"vdda2"
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],
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"GND_NETS": [
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"vssd1",
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"vssd2",
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"vssa1",
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"vssa2"
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"vssd1",
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"vssd2",
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"vssa1",
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"vssa2"
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],
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"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
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"pdk::sky130*": {
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"RT_MAX_LAYER": "met4",
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"DIE_AREA": "0 0 2920 3520",
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"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
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"scl::sky130_fd_sc_hd": {
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"CLOCK_PERIOD": 25
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},
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"scl::sky130_fd_sc_hdll": {
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"CLOCK_PERIOD": 10
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},
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"scl::sky130_fd_sc_hs": {
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"CLOCK_PERIOD": 8
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},
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"scl::sky130_fd_sc_ls": {
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"CLOCK_PERIOD": 10,
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"SYNTH_MAX_FANOUT": 5
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},
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"scl::sky130_fd_sc_ms": {
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"CLOCK_PERIOD": 10
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}
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"RT_MAX_LAYER": "met4",
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"DIE_AREA": "0 0 2920 3520",
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"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
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"scl::sky130_fd_sc_hd": {
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"CLOCK_PERIOD": 25
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},
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"scl::sky130_fd_sc_hdll": {
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"CLOCK_PERIOD": 10
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},
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"scl::sky130_fd_sc_hs": {
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"CLOCK_PERIOD": 8
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},
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"scl::sky130_fd_sc_ls": {
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"CLOCK_PERIOD": 10,
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"SYNTH_MAX_FANOUT": 5
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},
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"scl::sky130_fd_sc_ms": {
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"CLOCK_PERIOD": 10
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}
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},
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"pdk::gf180mcuC": {
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"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
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"FP_PDN_CHECK_NODES": 0,
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"FP_PDN_ENABLE_RAILS": 0,
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"RT_MAX_LAYER": "Metal4",
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"DIE_AREA": "0 0 3000 3000",
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"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
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"PL_OPENPHYSYN_OPTIMIZATIONS": 0,
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"DIODE_INSERTION_STRATEGY": 0,
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"MAGIC_WRITE_FULL_LEF": 0
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"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
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"FP_PDN_CHECK_NODES": 0,
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"FP_PDN_ENABLE_RAILS": 0,
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"RT_MAX_LAYER": "Metal4",
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"DIE_AREA": "0 0 3000 3000",
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"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
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"PL_OPENPHYSYN_OPTIMIZATIONS": 0,
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"DIODE_INSERTION_STRATEGY": 0,
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"MAGIC_WRITE_FULL_LEF": 0
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}
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}
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}
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