feat: add support for IHP PDK with OpenLane2 (for user projects)

This commit is contained in:
htfab
2025-03-06 08:10:24 +02:00
committed by Uri Shaked
parent 8f10bc8c74
commit 7d341a1195
19 changed files with 1623 additions and 1890 deletions
-13
View File
@@ -1,13 +0,0 @@
set clk_name core_clock
set clk_port_name clk
set clk_period 20
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
@@ -3,59 +3,59 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 212160 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 430 BY 1 STEP 480 0 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 202080 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 409 BY 1 STEP 480 0 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 504 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 480 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 504 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 480 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 93 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 88 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 53 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 50 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -63,175 +63,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
+ PLACED ( 187200 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
+ PLACED ( 191040 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
+ PLACED ( 183360 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
+ PLACED ( 179520 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
+ PLACED ( 175680 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
+ PLACED ( 171840 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
+ PLACED ( 168000 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
+ PLACED ( 164160 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
+ PLACED ( 160320 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
+ PLACED ( 156480 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
+ PLACED ( 152640 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
+ PLACED ( 148800 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
+ PLACED ( 144960 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
+ PLACED ( 141120 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
+ PLACED ( 137280 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
+ PLACED ( 133440 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
+ PLACED ( 129600 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
+ PLACED ( 125760 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
+ PLACED ( 121920 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
+ PLACED ( 56640 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
+ PLACED ( 52800 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
+ PLACED ( 48960 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
+ PLACED ( 45120 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
+ PLACED ( 41280 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
+ PLACED ( 37440 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
+ PLACED ( 33600 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
+ PLACED ( 29760 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
+ PLACED ( 87360 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
+ PLACED ( 83520 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
+ PLACED ( 79680 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
+ PLACED ( 75840 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
+ PLACED ( 72000 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
+ PLACED ( 68160 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
+ PLACED ( 64320 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
+ PLACED ( 60480 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
+ PLACED ( 118080 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
+ PLACED ( 114240 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
+ PLACED ( 110400 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
+ PLACED ( 106560 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
+ PLACED ( 102720 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
+ PLACED ( 98880 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
+ PLACED ( 95040 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
+ PLACED ( 91200 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,101 +3,101 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 642240 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 1326 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 202080 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 409 BY 1 STEP 480 0 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 1528 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 480 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 1528 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 480 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 281 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 88 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 160 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 50 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -105,175 +105,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
+ PLACED ( 183360 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,59 +3,59 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 427200 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 878 BY 1 STEP 480 0 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 419520 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 862 BY 1 STEP 480 0 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 1016 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 998 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 1016 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 998 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 187 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 184 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 107 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 105 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -63,175 +63,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
+ PLACED ( 187200 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
+ PLACED ( 191040 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
+ PLACED ( 183360 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
+ PLACED ( 179520 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
+ PLACED ( 175680 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
+ PLACED ( 171840 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
+ PLACED ( 168000 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
+ PLACED ( 164160 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
+ PLACED ( 160320 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
+ PLACED ( 156480 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
+ PLACED ( 152640 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
+ PLACED ( 148800 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
+ PLACED ( 144960 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
+ PLACED ( 141120 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
+ PLACED ( 137280 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
+ PLACED ( 133440 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
+ PLACED ( 129600 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
+ PLACED ( 125760 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
+ PLACED ( 121920 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
+ PLACED ( 56640 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
+ PLACED ( 52800 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
+ PLACED ( 48960 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
+ PLACED ( 45120 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
+ PLACED ( 41280 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
+ PLACED ( 37440 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
+ PLACED ( 33600 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
+ PLACED ( 29760 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
+ PLACED ( 87360 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
+ PLACED ( 83520 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
+ PLACED ( 79680 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
+ PLACED ( 75840 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
+ PLACED ( 72000 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
+ PLACED ( 68160 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
+ PLACED ( 64320 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
+ PLACED ( 60480 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
+ PLACED ( 118080 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
+ PLACED ( 114240 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
+ PLACED ( 110400 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
+ PLACED ( 106560 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
+ PLACED ( 102720 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
+ PLACED ( 98880 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
+ PLACED ( 95040 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
+ PLACED ( 91200 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,101 +3,101 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 212160 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 430 BY 1 STEP 480 0 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 419520 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 862 BY 1 STEP 480 0 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 504 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 998 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 504 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 998 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 93 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 184 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 53 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 105 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -105,175 +105,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
+ PLACED ( 183360 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,59 +3,59 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 642240 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1326 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 636960 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1315 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 1528 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 1516 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 1528 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 1516 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 281 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 279 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 160 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 159 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -63,175 +63,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
+ PLACED ( 187200 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
+ PLACED ( 191040 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
+ PLACED ( 183360 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
+ PLACED ( 179520 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
+ PLACED ( 175680 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
+ PLACED ( 171840 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
+ PLACED ( 168000 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
+ PLACED ( 164160 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
+ PLACED ( 160320 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
+ PLACED ( 156480 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
+ PLACED ( 152640 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
+ PLACED ( 148800 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
+ PLACED ( 144960 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
+ PLACED ( 141120 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
+ PLACED ( 137280 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
+ PLACED ( 133440 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
+ PLACED ( 129600 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
+ PLACED ( 125760 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
+ PLACED ( 121920 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
+ PLACED ( 56640 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
+ PLACED ( 52800 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
+ PLACED ( 48960 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
+ PLACED ( 45120 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
+ PLACED ( 41280 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
+ PLACED ( 37440 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
+ PLACED ( 33600 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
+ PLACED ( 29760 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
+ PLACED ( 87360 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
+ PLACED ( 83520 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
+ PLACED ( 79680 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
+ PLACED ( 75840 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
+ PLACED ( 72000 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
+ PLACED ( 68160 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
+ PLACED ( 64320 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
+ PLACED ( 60480 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
+ PLACED ( 118080 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
+ PLACED ( 114240 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
+ PLACED ( 110400 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
+ PLACED ( 106560 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
+ PLACED ( 102720 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
+ PLACED ( 98880 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
+ PLACED ( 95040 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
+ PLACED ( 91200 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,101 +3,101 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 427200 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 878 BY 1 STEP 480 0 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 636960 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 1315 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 1315 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 1315 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 1016 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 1516 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 1016 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 1516 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 187 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 279 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 107 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 159 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -105,175 +105,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
+ PLACED ( 183360 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,59 +3,59 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1287360 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 2670 BY 1 STEP 480 0 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 854400 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1768 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 3064 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 2034 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 3064 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 2034 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 564 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 374 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 213 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -63,175 +63,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
+ PLACED ( 187200 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
+ PLACED ( 191040 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
+ PLACED ( 183360 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
+ PLACED ( 179520 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
+ PLACED ( 175680 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
+ PLACED ( 171840 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
+ PLACED ( 168000 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
+ PLACED ( 164160 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
+ PLACED ( 160320 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
+ PLACED ( 156480 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
+ PLACED ( 152640 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
+ PLACED ( 148800 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
+ PLACED ( 144960 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
+ PLACED ( 141120 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
+ PLACED ( 137280 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
+ PLACED ( 133440 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
+ PLACED ( 129600 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
+ PLACED ( 125760 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
+ PLACED ( 121920 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
+ PLACED ( 56640 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
+ PLACED ( 52800 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
+ PLACED ( 48960 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
+ PLACED ( 45120 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
+ PLACED ( 41280 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
+ PLACED ( 37440 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
+ PLACED ( 33600 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
+ PLACED ( 29760 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
+ PLACED ( 87360 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
+ PLACED ( 83520 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
+ PLACED ( 79680 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
+ PLACED ( 75840 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
+ PLACED ( 72000 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
+ PLACED ( 68160 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
+ PLACED ( 64320 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
+ PLACED ( 60480 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
+ PLACED ( 118080 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
+ PLACED ( 114240 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
+ PLACED ( 110400 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
+ PLACED ( 106560 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
+ PLACED ( 102720 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
+ PLACED ( 98880 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
+ PLACED ( 95040 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
+ PLACED ( 91200 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,101 +3,101 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1717440 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 3566 BY 1 STEP 480 0 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 854400 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 1768 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 4088 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 2034 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 4088 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 2034 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 753 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 374 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 429 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 213 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -105,175 +105,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
+ PLACED ( 183360 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,59 +3,59 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 857280 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1774 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 1289280 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 2674 BY 1 STEP 480 0 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 2040 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 3069 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 2040 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 3069 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 376 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 565 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 214 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -63,175 +63,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
+ PLACED ( 187200 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
+ PLACED ( 191040 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
+ PLACED ( 183360 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
+ PLACED ( 179520 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
+ PLACED ( 175680 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
+ PLACED ( 171840 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
+ PLACED ( 168000 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
+ PLACED ( 164160 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
+ PLACED ( 160320 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
+ PLACED ( 156480 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
+ PLACED ( 152640 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
+ PLACED ( 148800 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
+ PLACED ( 144960 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
+ PLACED ( 141120 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
+ PLACED ( 137280 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
+ PLACED ( 133440 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
+ PLACED ( 129600 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
+ PLACED ( 125760 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
+ PLACED ( 121920 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
+ PLACED ( 56640 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
+ PLACED ( 52800 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
+ PLACED ( 48960 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
+ PLACED ( 45120 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
+ PLACED ( 41280 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
+ PLACED ( 37440 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
+ PLACED ( 33600 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
+ PLACED ( 29760 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
+ PLACED ( 87360 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
+ PLACED ( 83520 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
+ PLACED ( 79680 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
+ PLACED ( 75840 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
+ PLACED ( 72000 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
+ PLACED ( 68160 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
+ PLACED ( 64320 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
+ PLACED ( 60480 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
+ PLACED ( 118080 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
+ PLACED ( 114240 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
+ PLACED ( 110400 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
+ PLACED ( 106560 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
+ PLACED ( 102720 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
+ PLACED ( 98880 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
+ PLACED ( 95040 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
+ PLACED ( 91200 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
@@ -3,99 +3,99 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1287360 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 2670 BY 1 STEP 480 0 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 1289280 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 2674 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 2674 BY 1 STEP 480 0 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 3064 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 3069 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 3064 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 3069 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 564 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 565 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
@@ -105,175 +105,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
+ PLACED ( 183360 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
-285
View File
@@ -1,285 +0,0 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1717440 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 3566 BY 1 STEP 480 0 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 4088 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 4088 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 753 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 429 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
+285
View File
@@ -0,0 +1,285 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1724160 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 3580 BY 1 STEP 480 0 ;
TRACKS X 480 DO 3591 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 4104 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 3591 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 4104 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 3591 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 756 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 431 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 37440 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33600 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 29760 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
@@ -3,101 +3,101 @@ DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 857280 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 1774 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal1 ;
DIEAREA ( 0 0 ) ( 1724160 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 3580 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 3580 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 3580 BY 1 STEP 480 0 ;
TRACKS X 480 DO 3591 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 2040 STEP 420 LAYER Metal2 ;
TRACKS X 420 DO 4104 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal3 ;
TRACKS X 480 DO 3591 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 2040 STEP 420 LAYER Metal4 ;
TRACKS X 420 DO 4104 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal5 ;
TRACKS X 480 DO 3591 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 376 STEP 2280 LAYER TopMetal1 ;
TRACKS X 1460 DO 756 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 214 STEP 4000 LAYER TopMetal2 ;
TRACKS X 2000 DO 431 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
@@ -105,175 +105,175 @@ PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
+ PLACED ( 183360 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
-52
View File
@@ -1,52 +0,0 @@
#!/bin/bash
# Based on sg13g2-update.py from IHP
# Klayout
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp $ORFS_ROOT/flow/platforms/ihp-sg13g2/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt $ORFS_ROOT/flow/platforms/ihp-sg13g2/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.map $ORFS_ROOT/flow/platforms/ihp-sg13g2/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc $ORFS_ROOT/flow/platforms/ihp-sg13g2/drc/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc $ORFS_ROOT/flow/platforms/ihp-sg13g2/drc/
# LIB
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p35V_125C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p32V_m40C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p65V_m40C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p50V_25C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_dummy.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib $ORFS_ROOT/flow/platforms/ihp-sg13g2/lib/
# GDS
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds $ORFS_ROOT/flow/platforms/ihp-sg13g2/gds/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds $ORFS_ROOT/flow/platforms/ihp-sg13g2/gds/
# LEF
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef $ORFS_ROOT/flow/platforms/ihp-sg13g2/lef/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef $ORFS_ROOT/flow/platforms/ihp-sg13g2/lef/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lef/sg13g2_io.lef $ORFS_ROOT/flow/platforms/ihp-sg13g2/lef/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/lef/sg13g2_io_notracks.lef $ORFS_ROOT/flow/platforms/ihp-sg13g2/lef/
# Verilog
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v $ORFS_ROOT/flow/platforms/ihp-sg13g2/verilog/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v $ORFS_ROOT/flow/platforms/ihp-sg13g2/verilog/
# CDL
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x64_c2_bm_bist.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x64_c2_bm_bist.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_2048x64_c2_bm_bist.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_256x48_c2_bm_bist.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_256x64_c2_bm_bist.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_512x64_c2_bm_bist.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_64x64_c2_bm_bist.cdl $ORFS_ROOT/flow/platforms/ihp-sg13g2/cdl/
# Techmap
cp $IHP_PDK_ROOT/ihp-sg13g2/libs.tech/openlane/sg13g2_stdcell/latch_map.v $ORFS_ROOT/flow/platforms/ihp-sg13g2/cells_latch.v
-16
View File
@@ -1,16 +0,0 @@
# global connections
add_global_connection -net {VPWR} -pin_pattern {^VDD$} -power
add_global_connection -net {VPWR} -pin_pattern {^VDDPE$}
add_global_connection -net {VPWR} -pin_pattern {^VDDCE$}
add_global_connection -net {VGND} -pin_pattern {^VSS$} -ground
add_global_connection -net {VGND} -pin_pattern {^VSSE$}
global_connect
# voltage domains
set_voltage_domain -name {CORE} -power {VPWR} -ground {VGND}
# standard cell grid
define_pdn_grid -name {grid} -voltage_domains {CORE} -pins Metal5
add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -followpins
add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_core_ring
add_pdn_connect -grid {grid} -layers {Metal1 Metal5}
+12 -12
View File
@@ -1,12 +1,12 @@
1x1: "0 0 212.16 154.98"
1x2: "0 0 212.16 313.74"
2x1: "0 0 427.20 154.98"
2x2: "0 0 427.20 313.74"
3x1: "0 0 642.24 154.98"
3x2: "0 0 642.24 313.74"
4x1: "0 0 857.28 154.98"
4x2: "0 0 857.28 313.74"
6x1: "0 0 1287.36 154.98"
6x2: "0 0 1287.36 313.74"
8x1: "0 0 1717.44 154.98"
8x2: "0 0 1717.44 313.74"
1x1: "0 0 202.08 154.98"
1x2: "0 0 202.08 313.74"
2x1: "0 0 419.52 154.98"
2x2: "0 0 419.52 313.74"
3x1: "0 0 636.96 154.98"
3x2: "0 0 636.96 313.74"
4x1: "0 0 854.40 154.98"
4x2: "0 0 854.40 313.74"
6x1: "0 0 1289.28 154.98"
6x2: "0 0 1289.28 313.74"
8x1: "0 0 1724.16 154.98"
8x2: "0 0 1724.16 313.74"
+52 -238
View File
@@ -64,13 +64,9 @@ PINOUT_KEYS = [
SCRIPT_DIR = os.path.dirname(os.path.realpath(__file__))
with open(os.path.join(os.path.dirname(__file__), "tile_sizes.yaml"), "r") as stream:
tile_sizes = yaml.safe_load(stream)
class Args:
openlane2: bool
orfs: bool
ihp: bool
print_cell_summary: bool
print_cell_category: bool
@@ -355,30 +351,29 @@ class Project:
# metrics
def get_metrics_path(self):
if self.is_user_project:
if self.args.orfs:
return os.path.join(
self.local_dir,
"runs/wokwi/results/ihp-sg13g2/tt-submission/base/metrics.csv",
)
else:
return os.path.join(self.local_dir, "runs/wokwi/final/metrics.csv")
else:
return os.path.join(self.local_dir, "stats/metrics.csv")
def get_gl_path(self):
if self.is_user_project:
if self.args.orfs:
return os.path.join(
self.local_dir,
"runs/wokwi/results/ihp-sg13g2/tt-submission/base/6_final.v",
)
else:
return glob.glob(
os.path.join(self.local_dir, "runs/wokwi/final/nl/*.nl.v")
)[0]
else:
return os.path.join(self.local_dir, f"{self.info.top_module}.v")
def get_tile_sizes(self):
if self.args.ihp:
tile_sizes_yaml = "ihp/tile_sizes.yaml"
else:
tile_sizes_yaml = "tile_sizes.yaml"
with open(
os.path.join(os.path.dirname(__file__), tile_sizes_yaml), "r"
) as stream:
tile_sizes = yaml.safe_load(stream)
return tile_sizes
# name of the gds file
def get_macro_gds_filename(self):
return f"{self.info.top_module}.gds"
@@ -497,23 +492,17 @@ class Project:
self.check_ports()
logging.info("creating include file")
tiles = self.info.tiles
if self.args.orfs:
config = {
"DESIGN_NICKNAME": "tt-submission",
"DESIGN_NAME": self.info.top_module,
"PLATFORM": "ihp-sg13g2",
"VERILOG_FILES": [f"dir::{src}" for src in self.sources],
"FLOORPLAN_DEF": f"dir::../tt/ihp/def/tt_block_{tiles}.def",
"SDC_FILE": f"dir::../tt/ihp/constraint.sdc",
"PDN_TCL": f"dir::../tt/ihp/pdn.tcl",
}
else:
tile_sizes = self.get_tile_sizes()
die_area = tile_sizes[tiles]
if self.args.ihp:
def_template = f"dir::../tt/ihp/def/tt_block_{tiles}_pgvdd.def"
else:
def_template = f"dir::../tt/def/tt_block_{tiles}_pg.def"
config = {
"DESIGN_NAME": self.info.top_module,
"VERILOG_FILES": [f"dir::{src}" for src in self.sources],
"DIE_AREA": die_area,
"FP_DEF_TEMPLATE": f"dir::../tt/def/tt_block_{tiles}_pg.def",
"FP_DEF_TEMPLATE": def_template,
}
write_config(config, os.path.join(self.src_dir, "user_config"), ("json",))
@@ -533,50 +522,15 @@ class Project:
config = read_config("src/config", ("json", "tcl"))
user_config = read_config("src/user_config", ("json",))
if self.args.orfs and "PDN_TCL" in config:
del user_config["PDN_TCL"]
config.update(user_config)
if self.args.orfs:
write_config(config, "src/config_merged", ("mk",))
else:
write_config(config, "src/config_merged", ("json",))
if self.args.orfs:
shutil.rmtree("runs/wokwi", ignore_errors=True)
os.makedirs("runs/wokwi", exist_ok=True)
cdl = os.path.join(
self.local_dir,
"runs/wokwi/objects/ihp-sg13g2/tt-submission/base/6_final_concat.cdl",
)
harden_cmd = f"make -B -C $ORFS_ROOT/flow all generate_abstract {cdl}"
env = os.environ.copy()
if "ORFS_ROOT" not in env:
env["ORFS_ROOT"] = os.path.join(self.local_dir, "OpenROAD-flow-scripts")
if "OPENROAD_EXE" not in env:
openroad_exe = shutil.which("openroad")
if openroad_exe is None:
raise FileNotFoundError("OpenROAD executable not found")
env["OPENROAD_EXE"] = openroad_exe
if "YOSYS_EXE" not in env:
yosys_exe = shutil.which("yosys")
if yosys_exe is None:
raise FileNotFoundError("Yosys executable not found")
env["YOSYS_EXE"] = yosys_exe
if "IHP_PDK_ROOT" not in env:
env["IHP_PDK_ROOT"] = os.path.join(self.local_dir, "IHP-Open-PDK")
if "KLAYOUT_HOME" not in env:
env["KLAYOUT_HOME"] = os.path.join(
env["IHP_PDK_ROOT"], "ihp-sg13g2/libs.tech/klayout"
)
env["WORK_HOME"] = os.path.join(self.local_dir, "runs/wokwi")
env["DESIGN_HOME"] = self.src_dir
env["DESIGN_CONFIG"] = os.path.join(self.src_dir, "config_merged.mk")
else:
shutil.rmtree("runs/wokwi", ignore_errors=True)
os.makedirs("runs/wokwi", exist_ok=True)
arg_progress = "--hide-progress-bar" if "CI" in os.environ else ""
arg_pdk_root = '--pdk-root "$PDK_ROOT"' if "PDK_ROOT" in os.environ else ""
harden_cmd = f"python -m openlane {arg_pdk_root} --docker-no-tty --dockerized --run-tag wokwi --force-run-dir runs/wokwi {arg_progress} src/config_merged.json"
arg_pdk = "--manual-pdk --pdk ihp-sg13g2" if self.args.ihp else ""
harden_cmd = f"python -m openlane {arg_pdk_root} --docker-no-tty --dockerized {arg_pdk_root} {arg_pdk} --run-tag wokwi --force-run-dir runs/wokwi {arg_progress} src/config_merged.json"
env = os.environ.copy()
logging.debug(harden_cmd)
p = subprocess.run(harden_cmd, shell=True, env=env)
@@ -584,43 +538,7 @@ class Project:
logging.error("harden failed")
exit(1)
# Collect metrics
if self.args.orfs:
metrics = {}
metrics_inputs = glob.glob(
os.path.join(
self.local_dir,
"runs/wokwi/logs/ihp-sg13g2/tt-submission/base/*.json",
)
)
for metrics_input in metrics_inputs:
with open(metrics_input) as mf:
metrics.update(json.load(mf))
metrics_output = (
"runs/wokwi/results/ihp-sg13g2/tt-submission/base/metrics.csv"
)
with open(metrics_output, "w") as mf:
wr = csv.writer(mf)
wr.writerow(("Metric", "Value"))
wr.writerows(metrics.items())
# Fail if violations remain after detailed routing
if self.args.orfs:
if metrics["detailedroute__route__drc_errors"] > 0:
logging.error("error: detailed routing couldn't resolve all violations")
exit(1)
# DRC & LVS aren't included in the default ORFS flow
if self.args.orfs:
self.run_drc()
self.run_lvs()
# Write commit information
if self.args.orfs:
commit_id_json_path = (
"runs/wokwi/results/ihp-sg13g2/tt-submission/base/commit_id.json"
)
else:
commit_id_json_path = "runs/wokwi/final/commit_id.json"
with open(os.path.join(self.local_dir, commit_id_json_path), "w") as f:
json.dump(
@@ -635,31 +553,15 @@ class Project:
)
f.write("\n")
if self.args.orfs:
tool_queries = [
("yosys", "shell", "yosys -V"),
("openroad", "shell", "openroad -version"),
("klayout", "shell", "klayout -v"),
("orfs", "repo", env["ORFS_ROOT"]),
("ihp_pdk", "repo", env["IHP_PDK_ROOT"]),
]
tool_versions = {}
for tool_name, query_type, query_param in tool_queries:
if query_type == "shell":
tool_versions[tool_name] = subprocess.run(
query_param, shell=True, capture_output=True, text=True
).stdout.strip()
elif query_type == "repo":
tool_versions[tool_name] = (
Repo(os.path.join(self.local_dir, query_param)).commit().hexsha
)
with open("runs/wokwi/tool_versions.json", "w") as f:
json.dump(tool_versions, f, indent=2)
else:
resolved_json_path = "runs/wokwi/resolved.json"
config = json.load(open(os.path.join(self.local_dir, resolved_json_path)))
openlane_version = config["meta"]["openlane_version"]
if self.args.ihp:
pdk_repo = Repo(env["PDK_ROOT"])
pdk_repo_name = list(pdk_repo.remotes[0].urls)[0].split("/")[-1]
pdk_commit = pdk_repo.commit().hexsha
pdk_sources = f"{pdk_repo_name} {pdk_commit}"
else:
pdk_sources_file = os.path.join(
config["PDK_ROOT"], config["PDK"], "SOURCES"
)
@@ -668,6 +570,7 @@ class Project:
f"OpenLane2 {openlane_version}\n"
)
open("runs/wokwi/PDK_SOURCES", "w").write(pdk_sources)
if not self.args.ihp:
volare.enable(
volare.get_volare_home(), # uses PDK_ROOT if set, ~/.volare otherwise
{"sky130A": "sky130"}[config["PDK"]],
@@ -677,83 +580,10 @@ class Project:
os.chdir(cwd)
def run_drc(self):
if self.args.orfs:
gds_path = os.path.join(
self.local_dir,
"runs/wokwi/results/ihp-sg13g2/tt-submission/base/6_final.gds",
)
drc_script = os.path.join(
os.environ["IHP_PDK_ROOT"],
"ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc",
)
drc_report = os.path.join(
self.local_dir,
"runs/wokwi/reports/ihp-sg13g2/tt-submission/base/6_drc.lyrdb",
)
drc_log = os.path.join(
self.local_dir,
"runs/wokwi/logs/ihp-sg13g2/tt-submission/base/6_drc.log",
)
drc_cmd = f"klayout -b -rd in_gds={gds_path} -rd report_file={drc_report} -rd density=false -r {drc_script} | tee {drc_log}"
p = subprocess.run(drc_cmd, shell=True)
if p.returncode != 0:
logging.error("DRC job exited abnormally")
exit(1)
with open(drc_report) as f:
drc_ok = True
for line in f:
line = line.strip()
if re.match("<category>'([^']*)'</category>", line):
drc_ok = False
break
if drc_ok:
logging.info("DRC passed")
else:
logging.error("DRC failed")
exit(1)
else:
logging.warning(
"DRC is already included in OpenLane hardening job, skipping"
)
logging.warning("DRC is already included in OpenLane hardening job, skipping")
def run_lvs(self):
if self.args.orfs:
gds_path = os.path.join(
self.local_dir,
"runs/wokwi/results/ihp-sg13g2/tt-submission/base/6_final.gds",
)
cdl_path = os.path.join(
self.local_dir,
"runs/wokwi/objects/ihp-sg13g2/tt-submission/base/6_final_concat.cdl",
)
lvs_script = os.path.join(
os.environ["IHP_PDK_ROOT"],
"ihp-sg13g2/libs.tech/klayout/tech/lvs/sg13g2_full.lylvs",
)
lvs_report = os.path.join(
self.local_dir,
"runs/wokwi/reports/ihp-sg13g2/tt-submission/base/6_lvs.lvsdb",
)
lvs_log = os.path.join(
self.local_dir,
"runs/wokwi/logs/ihp-sg13g2/tt-submission/base/6_lvs.log",
)
lvs_cmd = f"klayout -b -rd in_gds={gds_path} -rd cdl_file={cdl_path} -rd report_file={lvs_report} -rd run_mode=deep -r {lvs_script} | tee {lvs_log}"
p = subprocess.run(lvs_cmd, shell=True)
if p.returncode != 0:
logging.error("LVS job exited abnormally")
exit(1)
with open(lvs_log) as f:
ok_msg = "Congratulations! Netlists match."
if any(ok_msg in line for line in f):
logging.info("LVS passed")
else:
logging.error("LVS failed")
exit(1)
else:
logging.warning(
"LVS is already included in OpenLane hardening job, skipping"
)
logging.warning("LVS is already included in OpenLane hardening job, skipping")
def create_fpga_bitstream(self):
logging.info(f"Creating FPGA bitstream for {self}")
@@ -875,11 +705,6 @@ class Project:
def get_final_gds_top_cells(self):
if "GDS_PATH" in os.environ:
gds_path = os.environ["GDS_PATH"]
elif self.args.orfs:
gds_path = os.path.join(
self.local_dir,
"runs/wokwi/results/ihp-sg13g2/tt-submission/base/6_final.gds",
)
else:
gds_path = glob.glob(
os.path.join(self.local_dir, "runs/wokwi/final/gds/*.gds")
@@ -919,7 +744,7 @@ class Project:
(67, 25), # 67/25 - Metal5.text
(126, 25), # 126/25 - TopMetal1.text
]
if self.args.orfs:
if self.args.ihp:
label_layers = ihp_label_layers
else:
label_layers = sky130_label_layers
@@ -974,7 +799,7 @@ class Project:
(51, 0), # 51/0 - HeatTrans.drawing
(189, 4), # 189/4 - prBoundary.boundary
]
if self.args.orfs:
if self.args.ihp:
buried_layers = ihp_buried_layers
else:
buried_layers = sky130_buried_layers
@@ -1037,9 +862,6 @@ class Project:
def print_warnings(self):
warnings: typing.List[str] = []
if self.args.orfs:
synth_log = "runs/wokwi/logs/ihp-sg13g2/tt-submission/base/1_1_yosys.log"
else:
synth_log_glob = "runs/wokwi/*-yosys-synthesis/yosys-synthesis.log"
synth_log = glob.glob(os.path.join(self.local_dir, synth_log_glob))[0]
with open(os.path.join(self.local_dir, synth_log)) as f:
@@ -1049,16 +871,11 @@ class Project:
if "WIDTHLABEL" not in line:
warnings.append(line.strip())
if self.args.orfs:
report = "runs/wokwi/logs/ihp-sg13g2/tt-submission/base/6_report.log"
with open(os.path.join(self.local_dir, report)) as f:
for line in f.readlines():
if line.startswith("Warning:"):
warnings.append(line.strip())
if self.args.ihp:
tt_corner = "nom_typ_1p20V_25C"
else:
sta_report_glob = (
"runs/wokwi/*-openroad-stapostpnr/nom_tt_025C_1v80/checks.rpt"
)
tt_corner = "nom_tt_025C_1v80"
sta_report_glob = f"runs/wokwi/*-openroad-stapostpnr/{tt_corner}/checks.rpt"
sta_report = glob.glob(os.path.join(self.local_dir, sta_report_glob))[0]
with open(os.path.join(self.local_dir, sta_report)) as f:
for line in f.readlines():
@@ -1072,22 +889,16 @@ class Project:
print(f"* {warning}")
def print_stats(self):
# ORFS & openlane2 don't have the same util% in its metrics as openlane1
if self.args.orfs:
util_log = "runs/wokwi/logs/ihp-sg13g2/tt-submission/base/3_3_place_gp.log"
else:
util_glob = (
"runs/wokwi/*-openroad-globalplacement/openroad-globalplacement.log"
)
util_glob = "runs/wokwi/*-openroad-globalplacement/openroad-globalplacement.log"
util_log = glob.glob(os.path.join(self.local_dir, util_glob))[0]
util_label = "[INFO GPL-0019] Util:"
util_line = next(line for line in open(util_log) if line.startswith(util_label))
util = util_line.removeprefix(util_label).strip()
if self.args.orfs:
try:
wire_length = self.metrics["route__wirelength"] # OpenROAD #2047
except KeyError:
wire_length = self.metrics["detailedroute__route__wirelength"]
else:
wire_length = self.metrics["route__wirelength"]
print("# Routing stats")
print()
@@ -1102,20 +913,20 @@ class Project:
Categories = typing.TypedDict(
"Categories", {"categories": typing.List[str], "map": typing.Dict[str, int]}
)
if self.args.orfs:
if self.args.ihp:
categories_file = "ihp/categories.json"
else:
categories_file = "categories.json"
with open(os.path.join(SCRIPT_DIR, categories_file)) as fh:
categories: Categories = json.load(fh)
if self.args.orfs:
if self.args.ihp:
ihp_defs = load_ihp_cells()
else:
sky130_defs = load_sky130_cells()
def _cell_url(name):
if self.args.orfs:
if self.args.ihp:
return _ihp_cell_url(ihp_defs[name]["doc_ref"])
else:
return _sky130_cell_url(name)
@@ -1133,7 +944,7 @@ class Project:
if count > 0:
total += count
cell_link = _cell_url(name)
if self.args.orfs:
if self.args.ihp:
description = ihp_defs[name]["description"]
else:
description = sky130_defs[name]["description"]
@@ -1196,17 +1007,20 @@ class Project:
def get_cell_counts_from_gl(self):
cell_count: typing.Dict[str, int] = {}
total = 0
if self.args.ihp:
cell_re = r"sg13g2_(?P<cell_name>\S+)_(?P<cell_drive>\d+)"
else:
cell_re = (
r"sky130_(?P<cell_lib>\S+)__(?P<cell_name>\S+)_(?P<cell_drive>\d+)"
)
with open(self.get_gl_path()) as fh:
for line in fh.readlines():
if self.args.orfs:
cell_re = r"sg13g2()_(\S+)_(\d+)"
else:
cell_re = r"sky130_(\S+)__(\S+)_(\d+)"
m = re.search(cell_re, line)
if m is not None:
total += 1
cell_lib = m.group(1)
cell_name = m.group(2)
gd = m.groupdict()
cell_lib = gd.get("cell_lib", "")
cell_name = gd["cell_name"]
assert cell_lib in ["fd_sc_hd", "ef_sc_hd", ""]
try:
cell_count[cell_name] += 1
+3 -3
View File
@@ -24,11 +24,11 @@ if __name__ == "__main__":
help="use openlane 2",
action="store_const",
const=True,
default=False,
default=True,
)
parser.add_argument(
"--orfs",
help="use ORFS",
"--ihp",
help="use IHP PDK",
action="store_const",
const=True,
default=False,