improve pdf generation, update hugo website generation

docs/doc_header.md

@@ -1,10 +1,10 @@
 ---
 title: |
   ![](pics/ttlogo.png){width=15cm}  
-    Tiny Tapeout 03 Datasheet
-subtitle: Project Repository [https://github.com/TinyTapeout/tinytapeout-03](https://github.com/TinyTapeout/tinytapeout-03)
+    Tiny Tapeout 3 Datasheet
+subtitle: Online Version [https://TinyTapeout.com/runs/TT03](https://TinyTapeout.com/runs/TT03)
 documentclass: scrartcl
-date: \today{}
+date: 24th April 2023
 geometry: "left=2cm,right=2cm,top=2cm,bottom=2.5cm"
 fontsize: 14pt
 mainfont: Latin Modern Sans
@@ -16,6 +16,51 @@ header-includes:
 
 \pagebreak
 
+# Tiny Tapeout
+
+Tiny Tapeout is a multi project chip platform that makes it easier and cheaper than ever to get ASIC designs manufactured.  Open source tools and process design kits are used, so no licenses or NDAs are needed. 
+
+In TT03, 249 open source designs are multiplexed to 16 general purpose input/output (GPIO) pins, and after manufacture the chips are mounted to a demonstration board for easy testing. Each chip contains every design, which can be activated and tested in turn.
+
+Each participant submits documentation for their design, collected to form this datasheet! We hope you enjoy experimenting with the chip and finding interesting designs to play with.
+
+# Project statistics
+
+* 100 projects submitted, 149 projects added from TT02
+* build time for all projects 22.68 hours
+* total cells 79674
+* max cells 1287 for project 072
+* max utilisation 59.95% for project 044
+* total wire length 4079 mm
+* 94 used Wokwi, 135 Verilog, 1 myhdl, 7 Amaranth, spade 1, xls 2, migen 1, systemverilog 3, mixed radix circuit synthesis (mrcs) 1, chisel 1.
+* top 10 tags:
+    - test      : 21
+    - experiment: 6
+    - cpu       : 6
+    - timer     : 5
+    - risc      : 5
+    - game      : 4
+    - pwm       : 4
+    - music     : 4
+    - counter   : 4
+
+\pagebreak
+
+# PCB
+
+* Designs are selected with the 'select project' switches.
+* Inputs are set with the 'input' switches.
+* The clock button is wired to input0.
+* The reset button is wired to input1.
+* Outputs are displayed on the 7 segment LED.
+* A clock can be automatically generated by connecting the 'slow enable' header - see [the clock divider](#clock-divider) for more information.
+
+![PCB](pics/pcb.jpg)
+
+See [https://tinytapeout.com/specs/pcb-tt123/](https://tinytapeout.com/specs/pcb-tt123/) for more details.
+
+\pagebreak
+
 # Render of whole chip
 
 ![Full GDS](pics/tinytapeout_numbered.png)

docs/doc_template.md

@@ -1,5 +1,7 @@
 ## {index} : {title}
 
+Set project to 0b {binary_spaces}
+
 {picture_link}
 
 * Author: {author}

docs/hugo_index_template.md

@@ -1,6 +1,6 @@
 ---
-title: "Tiny Tapeout 03"
-weight: 20
+title: "Tiny Tapeout 3"
+weight: 30
 description: 249 designs, closed 24th April 2023
 ---
 
@@ -17,7 +17,8 @@ description: 249 designs, closed 24th April 2023
 
 * Launched: 1 March 2023
 * Submission closed: 24 April 2023
-* Submitted to Efabless 2304C chipIgnite shuttle using Skywater 130nm open source PDK
+* Submitted to Efabless [2304C chipIgnite](https://efabless.com/shuttle-status) shuttle using Skywater 130nm open source PDK
+* Chips expected October 2023, PCBs expected December 2023
 
 # Project statistics
 

docs/hugo_template.md

@@ -4,12 +4,13 @@ title: "{index} {title}"
 weight: {weight}
 ---
 
-## {index} : {title}
+## {index} : 0b {binary_spaces} : {title}
+
+{{{{< tt-scanchain-switches "{binary}" >}}}}
 
 * Author: {author}
 * Description: {description}
 * [GitHub repository]({git_url})
-* [Most recent GDS build]({git_action})
 * {project_type} project
 * [Extra docs]({doc_link})
 * Clock: {clock_hz} Hz

docs/silicon_validation.md

@@ -0,0 +1,21 @@
+# Silicon Validation
+
+TT03 silicon was received in January 2024. The only differences expected between TT02 and TT03 were the designs and an improved scanchain. See the section on the [scan chain](#scan-chain) for more information on the changes. 
+
+In TT02 the top speed was limited to around 20 MHz due to the long scan chain and using 2 buffers for each design. The trace shows input clock in yellow and output at the end of the chain in blue.
+
+![tt02 clock out](pics/tt02_clock_out.png)
+
+The TT03 trace shows a much more symmetric output pulse.
+
+![tt03 clock out](pics/tt03_clock_out.png)
+
+The TT03 scanchain was tested up to 40 MHz. The trace shows input clock in blue and output at the end of the chain in yellow.
+
+![40M](pics/scan40M.png)
+
+## Scan chain frequency for TT03
+
+It's likely the chain could be run faster with an external driver, but because the RISCV CPU inside Caravel is being used to setup the GPIOs, it also needs to work at the chosen frequency. Caravel works up to 50MHz, so 40MHz was chosen as a safe lower value for the new oscillator frequency.
+
+This means that a design's IO will be updated at 8 KHz, and hence a maximum input clock of 4 KHz.

documentation.py

@@ -60,6 +60,9 @@ class Docs():
         with open(os.path.join(self.script_dir, 'docs', 'STA.md')) as fh:
             doc_sta = fh.read()
 
+        with open(os.path.join(self.script_dir, 'docs', 'silicon_validation.md')) as fh:
+            doc_silicon_validation = fh.read()
+
         with open(os.path.join(self.script_dir, 'docs', 'CREDITS.md')) as fh:
             doc_credits = fh.read()
 
@@ -72,6 +75,7 @@ class Docs():
                 yaml_data = project.get_project_doc_yaml()
 
                 yaml_data['index'] = project.index
+                yaml_data['binary_spaces'] = self.convert_to_9_bit_binary(project.index)
 
                 logging.info(f"building datasheet for {project}")
                 # handle pictures
@@ -98,6 +102,8 @@ class Docs():
             fh.write("\n\clearpage\n")
             fh.write(doc_sta)
             fh.write("\n\clearpage\n")
+            fh.write(doc_silicon_validation)
+            fh.write("\n\clearpage\n")
             fh.write(doc_credits)
 
         logging.info(f'wrote markdown to {self.args.dump_markdown}')
@@ -109,6 +115,18 @@ class Docs():
             if p.returncode != 0:
                 logging.error("pdf command failed")
 
+    @staticmethod
+    def convert_to_9_bit_binary(num, spaces=True):
+        binary_str = bin(int(num))[2:]
+        binary_str = binary_str.zfill(9)
+        # Insert spaces between groups of 3 bits
+        if spaces:
+            joint = ' '
+        else:
+            joint = ''
+        formatted_binary = joint.join([binary_str[i:i+3] for i in range(0, 9, 3)])
+        return formatted_binary
+
     def build_hugo_content(self):
         hugo_root = self.args.build_hugo_content
         hugo_images = os.path.join(hugo_root, 'images')
@@ -143,8 +161,10 @@ class Docs():
                     os.makedirs(project_image_dir)
                     yaml_data = project.get_project_doc_yaml()
                     yaml_data['index'] = project.index
+                    yaml_data['binary_spaces'] = self.convert_to_9_bit_binary(project.index)
+                    yaml_data['binary'] = self.convert_to_9_bit_binary(project.index, spaces=False)
                     yaml_data['weight'] = project.index + 1
-                    yaml_data['git_action'] = project.get_latest_action_url()
+                    #yaml_data['git_action'] = project.get_latest_action_url()
                     yaml_data['picture_link'] = ''
                     if yaml_data['picture']:
                         picture_name = yaml_data['picture']