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https://github.com/TinyTapeout/tt-support-tools.git
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feat(fpga): add support for the new FabricFox devkit
* TT FPGA tool, prelim import * config.ini manager, prelim * bitstream uploads and FPGA config.ini management Contributed by @psychogenic, with minor edits by @htfab
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@@ -2,7 +2,7 @@ import json
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import os
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from typing import Dict, List, Literal, Pattern, Protocol, Tuple, TypedDict, Union
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TechName = Literal["sky130A", "ihp-sg13g2", "gf180mcuD"]
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TechName = Literal["sky130A", "ihp-sg13g2", "gf180mcuD", "fpgaUp5k"]
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class CellDefinition(TypedDict):
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@@ -16,6 +16,7 @@ class PDKVersionInfo(TypedDict):
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class Tech(Protocol):
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is_fpga: bool
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def_suffix: str
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librelane_pdk_args: str
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tt_corner: str
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@@ -65,6 +66,7 @@ def parse_openpdks_pdk_version(
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class Sky130Tech(Tech):
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is_fpga = False
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def_suffix = "pg"
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librelane_pdk_args = ""
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tt_corner = "nom_tt_025C_1v80"
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@@ -124,6 +126,7 @@ class Sky130Tech(Tech):
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class IHPTech(Tech):
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is_fpga = False
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def_suffix = "pgvdd"
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librelane_pdk_args = "--pdk ihp-sg13g2"
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tt_corner = "nom_typ_1p20V_25C"
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@@ -177,6 +180,7 @@ class IHPTech(Tech):
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class GF180MCUDTech(Tech):
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is_fpga = False
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def_suffix = "pgvdd"
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librelane_pdk_args = "--pdk gf180mcuD"
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tt_corner = "nom_tt_025C_3v30"
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@@ -248,8 +252,33 @@ class GF180MCUDTech(Tech):
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return cells
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class FpgaTech(Tech):
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is_fpga = True
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# dummy values to keep the type checker happy
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def_suffix = ""
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librelane_pdk_args = ""
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tt_corner = ""
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cell_regexp = r""
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netlist_type = "nl"
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project_top_metal_layer = ""
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librelane_config = {}
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label_layers = []
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buried_layers = []
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scramble_cells = None
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mux_config_yaml_name = ""
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mux_macros = []
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extra_logo_macros = []
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prboundary_layer = (0, 0)
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logo_layer = (0, 0)
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logo_layer_name = ""
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logo_pixel_size = 0
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read_pdk_version = Tech.read_pdk_version
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load_cell_definitions = Tech.load_cell_definitions
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tech_map: dict[TechName, Tech] = {
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"ihp-sg13g2": IHPTech(),
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"gf180mcuD": GF180MCUDTech(),
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"sky130A": Sky130Tech(),
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"fpgaUp5k": FpgaTech(),
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}
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