mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
feat(precheck): add support for 3v3 templates
This commit is contained in:
htfab
+174
-52
@@ -107,50 +107,69 @@ def gds_invalid_macro_name(tmp_path_factory: pytest.TempPathFactory):
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return str(gds_file)
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class PortRect:
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def __init__(
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self, layer: str, bottom_left: tuple[int, int], top_right: tuple[int, int]
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):
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self.layer = layer
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self.lx, self.by = bottom_left
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self.rx, self.ty = top_right
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class CompoundPort:
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def __init__(self, name: str, rects: list[PortRect]):
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self.name = name
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self.port_use = "ground" if name == "VGND" else "power"
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self.port_class = "bidirectional"
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self.rects = rects
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class SimplePort(CompoundPort):
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def __init__(self, name: str, *rect_args: list):
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super().__init__(name, [PortRect(*rect_args)])
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def generate_analog_example(
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tcl_file: str,
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gds_file: str,
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lef_file: str,
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toplevel: str,
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vpwr_layer: str,
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vpwr_boxes: str,
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vgnd_layer: str,
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vgnd_boxes: str,
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extra_ports: list[CompoundPort],
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):
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with open(tcl_file, "w") as f:
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f.write(
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textwrap.dedent(
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def tcl_append(s):
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f.write(textwrap.dedent(s))
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tcl_append(
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f"""
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def read ../def/analog/tt_analog_1x2.def
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cellname rename tt_um_template {toplevel}
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"""
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)
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for port in extra_ports:
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for rect in port.rects:
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tcl_append(
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f"""
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box {rect.lx} {rect.by} {rect.rx} {rect.ty}
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paint {rect.layer}
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label {port.name} FreeSans {rect.layer}
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"""
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)
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tcl_append(
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f"""
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def read ../def/analog/tt_analog_1x2.def
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cellname rename tt_um_template {toplevel}
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# VPWR
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foreach vpwr_box {{ {vpwr_boxes} }} {{
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box {{*}}$vpwr_box
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paint {vpwr_layer}
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label VPWR FreeSans {vpwr_layer}
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}}
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port VPWR makeall n
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port VPWR use power
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port VPWR class bidirectional
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port {port.name} makeall n
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port {port.name} use {port.port_use}
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port {port.name} class {port.port_class}
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port conn n s e w
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# VGND
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foreach vgnd_box {{ {vgnd_boxes} }} {{
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box {{*}}$vgnd_box
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paint {vgnd_layer}
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label VGND FreeSans {vgnd_layer}
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}}
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port VGND makeall n
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port VGND use ground
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port VGND class bidirectional
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port conn n s e w
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# Export
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gds write {gds_file}
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lef write {lef_file}
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"""
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)
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tcl_append(
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f"""
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# Export
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gds write {gds_file}
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lef write {lef_file}
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"""
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)
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magic = subprocess.run(
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@@ -179,10 +198,30 @@ def gds_lef_analog_example(tmp_path_factory: pytest.TempPathFactory):
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str(gds_file),
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str(lef_file),
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"TEST_analog_example",
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"met4",
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"{100 500 250 22076}",
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"met4",
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"{4900 500 5050 22076}",
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[
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SimplePort("VDPWR", "met4", (100, 500), (250, 22076)),
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SimplePort("VGND", "met4", (4900, 500), (5050, 22076)),
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],
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)
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return str(gds_file), str(lef_file)
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@pytest.fixture(scope="session")
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def gds_lef_analog_power_compat(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS and LEF using the 1x2 analog template, with VPWR instead of VDPWR."""
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tcl_file = tmp_path_factory.mktemp("tcl") / "TEST_analog_power_compat.tcl"
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_analog_power_compat.gds"
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lef_file = tmp_path_factory.mktemp("lef") / "TEST_analog_power_compat.lef"
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generate_analog_example(
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str(tcl_file),
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str(gds_file),
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str(lef_file),
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"TEST_analog_power_compat",
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[
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SimplePort("VPWR", "met4", (100, 500), (250, 22076)),
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SimplePort("VGND", "met4", (4900, 500), (5050, 22076)),
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],
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)
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return str(gds_file), str(lef_file)
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@@ -199,10 +238,10 @@ def gds_lef_analog_wrong_vgnd(tmp_path_factory: pytest.TempPathFactory):
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str(gds_file),
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str(lef_file),
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"TEST_analog_wrong_vgnd",
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"met4",
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"{100 500 250 22076}",
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"met3",
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"{4900 500 5250 12076}",
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[
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SimplePort("VDPWR", "met4", (100, 500), (250, 22076)),
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SimplePort("VGND", "met3", (4900, 500), (5250, 12076)),
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],
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)
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return str(gds_file), str(lef_file)
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@@ -219,10 +258,10 @@ def gds_lef_analog_overlapping_vgnd(tmp_path_factory: pytest.TempPathFactory):
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str(gds_file),
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str(lef_file),
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"TEST_analog_overlapping_vgnd",
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"met4",
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"{100 500 250 22076}",
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"met4",
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"{349 20 549 22504}",
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[
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SimplePort("VDPWR", "met4", (100, 500), (250, 22076)),
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SimplePort("VGND", "met4", (3000, 20), (3200, 22504)),
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],
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)
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return str(gds_file), str(lef_file)
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@@ -230,19 +269,46 @@ def gds_lef_analog_overlapping_vgnd(tmp_path_factory: pytest.TempPathFactory):
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@pytest.fixture(scope="session")
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def gds_lef_analog_compound_vgnd(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS and LEF using the 1x2 analog template, with VGND consisting of two rectangles."""
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tcl_file = tmp_path_factory.mktemp("tcl") / "TEST_analog_example.tcl"
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_analog_example.gds"
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lef_file = tmp_path_factory.mktemp("lef") / "TEST_analog_example.lef"
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tcl_file = tmp_path_factory.mktemp("tcl") / "TEST_analog_compound_vgnd.tcl"
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_analog_compound_vgnd.gds"
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lef_file = tmp_path_factory.mktemp("lef") / "TEST_analog_compound_vgnd.lef"
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generate_analog_example(
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str(tcl_file),
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str(gds_file),
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str(lef_file),
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"TEST_analog_compound_vgnd",
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"met4",
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"{100 500 250 22076}",
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"met4",
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"{4900 500 5050 12076} {4900 12000 5050 22076}",
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[
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SimplePort("VDPWR", "met4", (100, 500), (250, 22076)),
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CompoundPort(
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"VGND",
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[
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PortRect("met4", (4900, 500), (5050, 12076)),
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PortRect("met4", (4900, 12000), (5050, 22076)),
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],
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),
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],
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)
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return str(gds_file), str(lef_file)
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@pytest.fixture(scope="session")
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def gds_lef_analog_example_3v3(tmp_path_factory: pytest.TempPathFactory):
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"""Creates a GDS and LEF using the 1x2 analog template."""
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tcl_file = tmp_path_factory.mktemp("tcl") / "TEST_analog_example_3v3.tcl"
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gds_file = tmp_path_factory.mktemp("gds") / "TEST_analog_example_3v3.gds"
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lef_file = tmp_path_factory.mktemp("lef") / "TEST_analog_example_3v3.lef"
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generate_analog_example(
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str(tcl_file),
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str(gds_file),
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str(lef_file),
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"TEST_analog_example_3v3",
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[
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SimplePort("VDPWR", "met4", (100, 500), (250, 22076)),
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SimplePort("VAPWR", "met4", (2500, 500), (2650, 22076)),
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SimplePort("VGND", "met4", (4900, 500), (5050, 22076)),
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],
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)
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return str(gds_file), str(lef_file)
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@@ -317,6 +383,18 @@ def test_pin_analog_example(gds_lef_analog_example: tuple[str, str]):
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lef_file,
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"../def/analog/tt_analog_1x2.def",
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"TEST_analog_example",
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False,
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)
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def test_pin_analog_power_compat(gds_lef_analog_power_compat: tuple[str, str]):
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gds_file, lef_file = gds_lef_analog_power_compat
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precheck.pin_check(
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gds_file,
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lef_file,
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"../def/analog/tt_analog_1x2.def",
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"TEST_analog_power_compat",
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False,
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)
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@@ -331,6 +409,7 @@ def test_pin_analog_wrong_vgnd(gds_lef_analog_wrong_vgnd: tuple[str, str]):
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lef_file,
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"../def/analog/tt_analog_1x2.def",
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"TEST_analog_wrong_vgnd",
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False,
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)
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@@ -345,6 +424,7 @@ def test_pin_analog_overlapping_vgnd(gds_lef_analog_overlapping_vgnd: tuple[str,
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lef_file,
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"../def/analog/tt_analog_1x2.def",
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"TEST_analog_overlapping_vgnd",
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False,
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)
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@@ -355,4 +435,46 @@ def test_pin_analog_compound_vgnd(gds_lef_analog_compound_vgnd: tuple[str, str])
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lef_file,
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"../def/analog/tt_analog_1x2.def",
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"TEST_analog_compound_vgnd",
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False,
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)
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def test_pin_analog_example_3v3(gds_lef_analog_example_3v3: tuple[str, str]):
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gds_file, lef_file = gds_lef_analog_example_3v3
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precheck.pin_check(
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gds_file,
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lef_file,
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"../def/analog/tt_analog_1x2.def",
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"TEST_analog_example_3v3",
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True,
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)
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def test_pin_analog_3v3_mismatch1(gds_lef_analog_example: tuple[str, str]):
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with pytest.raises(
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precheck.PrecheckFailure,
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match="Some ports are missing or have wrong dimensions",
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):
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gds_file, lef_file = gds_lef_analog_example
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precheck.pin_check(
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gds_file,
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lef_file,
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"../def/analog/tt_analog_1x2.def",
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"TEST_analog_example",
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True,
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)
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def test_pin_analog_3v3_mismatch2(gds_lef_analog_example_3v3: tuple[str, str]):
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with pytest.raises(
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precheck.PrecheckFailure,
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match="Some ports are missing or have wrong dimensions",
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):
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gds_file, lef_file = gds_lef_analog_example_3v3
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precheck.pin_check(
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gds_file,
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lef_file,
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"../def/analog/tt_analog_1x2.def",
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"TEST_analog_example_3v3",
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False,
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)
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