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wip hugo docs

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Matt Venn
2023-03-17 16:59:56 +01:00
parent 9b82e7721e
commit 906cd09762
2 changed files with 13 additions and 30 deletions
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docs/hugo_index_template.md
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--- ---
title: "Tiny Tapeout 02" title: "Tiny Tapeout 03"
weight: 10 weight: 20
description: Overview description: Overview
--- ---
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# Design details # Design details
* [Github repository](https://github.com/TinyTapeout/tinytapeout-02) * [Github repository](https://github.com/TinyTapeout/tinytapeout-03)
* [PDF datasheet](https://github.com/TinyTapeout/tinytapeout-02/raw/tt02/datasheet.pdf) * [PDF datasheet](https://github.com/TinyTapeout/tinytapeout-03/raw/tt03/datasheet.pdf)
* [Verification](https://github.com/TinyTapeout/tinytapeout-02/blob/tt02/VERIFICATION.md) * [Verification](https://github.com/TinyTapeout/tinytapeout-03/blob/tt03/VERIFICATION.md)
* [Efabless MPW submission](https://platform.efabless.com/projects/1410) * [Efabless MPW submission](https://platform.efabless.com/projects/1971)
# Launch stats # Launch stats
* Launched: 9 November 2023 * Launched: 1 March 2023
* Submission closed: 2 December 2023 * Submission closed: 24 April 2023
* Submitted to Efabless 2211Q chipIgnite shuttle using Skywater 130nm open source PDK * Submitted to Efabless 2304C chipIgnite shuttle using Skywater 130nm open source PDK
# Project statistics # Project statistics
* 165 projects submitted. Each project is 150 x 170um * TBA
* Youngest submitter: [4 years old](https://tinytapeout.com/runs/tt02/031)
* 64 used Wokwi graphical editor, 82 Verilog, 5 Amaranth, 1 Chisel
* 39935 standard cells used across all projects.
* Most cells used in a design was 1105, the least was 8.
* Max utilisation was 52%
* Total wire length 2024 mm.
## Whole die render ## Whole die render
![whole die](images/tinytapeout.png) ![whole die](images/tinytapeout-03.png)
# Project Showcase # Project Showcase
## Wokwi projects * TBA
* [UART-CC](https://tinytapeout.com/runs/tt02/057)
* [Nano-neuron](https://tinytapeout.com/runs/tt02/066)
* [Worm in a Maze](https://tinytapeout.com/runs/tt02/084)
* [Wolf sheep cabbage river crossing puzzle ASIC design](https://tinytapeout.com/runs/tt02/111)
## HDL projects
* [Avalon Semiconductors 'TBB1143' Programmable Sound Generator](https://tinytapeout.com/runs/tt02/024/)
* [Pi (π) to 1000+ decimal places](https://tinytapeout.com/runs/tt02/036)
* [FPGA test](https://tinytapeout.com/runs/tt02/090)
* [RV8U - 8-bit RISC-V Microcore Processor](https://tinytapeout.com/runs/tt02/107)
* [8-bit CPU](https://tinytapeout.com/runs/tt02/085/)
# Testimonials / Endorsements # Testimonials / Endorsements
documentation.py
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index_template = fh.read() index_template = fh.read()
# copy image # copy image
shutil.copyfile('tinytapeout.png', os.path.join(hugo_images, 'tinytapeout.png')) shutil.copyfile('pics/tinytapeout.png', os.path.join(hugo_images, 'tinytapeout-03.png')) #todo fix hardcoded run
# index page # index page
logging.info("building pages - can take a minute as fetching latest GDS action URLs for all projects") logging.info("building pages - can take a minute as fetching latest GDS action URLs for all projects")