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https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
tested user project stuff, docs, metrics, working on caravel
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+18
-2
@@ -63,7 +63,7 @@ class Project():
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exit(1)
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def check_num_cells(self):
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num_cells = self.get_cell_count_from_gl()
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num_cells = self.get_cell_count_from_synth()
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if self.is_hdl():
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if num_cells < 20:
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logging.warning(f"{self} only has {num_cells} cells")
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@@ -486,8 +486,24 @@ class Project():
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cell_links = [f'[{name}]({CELL_URL}{name})' for name in cat_dict['examples']]
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print(f'|{cat_name} | {" ".join(cell_links)} | {cat_dict["count"]}|')
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# get cell count from synth report
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def get_cell_count_from_synth(self):
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num_cells = 0
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try:
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yosys_report = glob.glob(f'{self.local_dir}/runs/wokwi/reports/synthesis/1-synthesis.*0.stat.rpt')[0] # can't open a file with \ in the path
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with open(yosys_report) as fh:
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for line in fh.readlines():
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m = re.search(r'Number of cells:\s+(\d+)', line)
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if m is not None:
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num_cells = int(m.group(1))
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except IndexError:
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logging.warning(f"couldn't open yosys cell report for cell checking {self}")
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return num_cells
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# Parse the lib, cell and drive strength an OpenLane gate-level Verilog file
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def get_cell_count_from_gl(self):
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def get_cell_counts_from_gl(self):
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cell_count = {}
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total = 0
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gl_files = glob.glob(os.path.join(self.local_dir, 'runs/wokwi/results/final/verilog/gl/*.nl.v'))
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