diff --git a/caravel_template/dump_pic.rb b/caravel_template/dump_pic.rb
index 7bdf5c9..c486396 100644
--- a/caravel_template/dump_pic.rb
+++ b/caravel_template/dump_pic.rb
@@ -1 +1 @@
-RBA::Application.instance.main_window.current_view.save_image("./tinytapeout.png",2000,2000)
+RBA::Application.instance.main_window.current_view.save_image("./pics/tinytapeout.png",2000,2000)
diff --git a/caravel_template/klayoutrc b/caravel_template/klayoutrc
index f08f5ef..d480f0f 100644
--- a/caravel_template/klayoutrc
+++ b/caravel_template/klayoutrc
@@ -152,7 +152,7 @@
16
0
- '/home/matt/work/asic-workshop/shuttle6/zero_to_asic_mpw6/gds/user_project_wrapper.gds.gz' '/home/matt/work/asic-workshop/shuttle7/zero_to_asic_mpw7/gds/user_project_wrapper.gds.gz' '/home/matt/work/asic-workshop/shuttle7/tinytapeout-02/gds/user_project_wrapper.gds' '/home/matt/work/asic-workshop/shuttle8/tinytapeout-02/gds/user_project_wrapper.gds' '/home/matt/work/asic-workshop/shuttle9/caravel_user_project/gds/user_project_wrapper.gds'
+ '/home/matt/work/asic-workshop/shuttle6/zero_to_asic_mpw6/gds/user_project_wrapper.gds.gz' '/home/matt/work/asic-workshop/shuttle7/zero_to_asic_mpw7/gds/user_project_wrapper.gds.gz' '/home/matt/work/asic-workshop/shuttle7/tinytapeout-02/gds/user_project_wrapper.gds' '/home/matt/work/asic-workshop/shuttle8/tinytapeout-02/gds/user_project_wrapper.gds' '/home/matt/work/asic-workshop/shuttle9/caravel_user_project/gds/user_project_wrapper.gds' '/home/matt/work/asic-workshop/shuttle9/tinytapeout-03/gds/user_project_wrapper.gds'
false
true
false
diff --git a/docs/CREDITS.md b/docs/CREDITS.md
index b5eefdf..7608e37 100644
--- a/docs/CREDITS.md
+++ b/docs/CREDITS.md
@@ -1,6 +1,6 @@
# Sponsored by
-[](https://efabless.com/)
+[](https://efabless.com/)
# Team
diff --git a/docs/doc_header.md b/docs/doc_header.md
index 170b0d6..58be003 100644
--- a/docs/doc_header.md
+++ b/docs/doc_header.md
@@ -1,6 +1,6 @@
---
title: |
- {width=15cm}
+ {width=15cm}
Tiny Tapeout 03 Datasheet
subtitle: Project Repository [https://github.com/TinyTapeout/tinytapeout-03](https://github.com/TinyTapeout/tinytapeout-03)
documentclass: scrartcl
@@ -18,7 +18,7 @@ header-includes:
# Render of whole chip
-
+
\pagebreak
diff --git a/project.py b/project.py
index cf38671..5613123 100644
--- a/project.py
+++ b/project.py
@@ -248,6 +248,9 @@ class Project():
def get_macro_lef_filename(self):
return f"{self.top_module}.lef"
+ def get_macro_spef_filename(self):
+ return f"{self.top_module}.spef"
+
# for GL sims & blackboxing
def get_gl_verilog_filename(self):
return f"{self.top_module}.v"
@@ -266,10 +269,10 @@ class Project():
def get_git_url(self):
return self.git_url
- # todo add spef
def copy_files_to_caravel(self):
files = [
(f"runs/wokwi/results/final/gds/{self.get_macro_gds_filename()}", f"gds/{self.get_macro_gds_filename()}"),
+ (f"runs/wokwi/results/final/spef/{self.get_macro_spef_filename()}", f"spef/{self.get_macro_spef_filename()}"),
(f"runs/wokwi/results/final/lef/{self.get_macro_lef_filename()}", f"lef/{self.get_macro_lef_filename()}"),
(f"runs/wokwi/results/final/verilog/gl/{self.get_gl_verilog_filename()}", f"verilog/gl/{self.get_gl_verilog_filename()}"),
(f"src/{self.top_verilog_filename}", f"verilog/rtl/{self.get_top_verilog_filename()}"),