From b02cc19e78a4bba1950a47ad2dac1d99b15f598b Mon Sep 17 00:00:00 2001
From: Uri Shaked <uri@urishaked.com>
Date: Sun, 10 Sep 2023 20:23:48 +0300
Subject: [PATCH] fix: shuttle config fails as tt_um_chip_rom verilog is
 missing

The Chip ROM is now auto generated, so the GL verilog only exists after we configure the shuttle
---
 project.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/project.py b/project.py
index 1ac8039..b236233 100644
--- a/project.py
+++ b/project.py
@@ -44,6 +44,8 @@ class Project():
 
     def check_ports(self):
         top = self.get_macro_name()
+        if not self.is_user_project and top == "tt_um_chip_rom":
+            return # Chip ROM is auto generated, so we don't have the verilog yet
         sources = [os.path.join(self.src_dir, src) for src in self.src_files]
         source_list = " ".join(sources)