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refactor!(tt_tool): use same dir for wokwi_test as for test

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htfab
2024-06-06 07:33:49 +03:00
committed by Uri Shaked
parent 6924b7464b
commit b36543e651
2 changed files with 9 additions and 3 deletions
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testing/src-tpl/Makefile
+2 -1
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@@ -4,12 +4,13 @@
# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog
SRC_DIR = $(PWD)/../src
# normal simulation
ifneq ($(GATES),yes)
# this is the only part you should need to modify:
VERILOG_SOURCES += $(PWD)/cells.v $(PWD)/tt_um_wokwi_WOKWI_ID.v $(PWD)/test_wokwi.v
VERILOG_SOURCES += $(SRC_DIR)/cells.v $(SRC_DIR)/tt_um_wokwi_WOKWI_ID.v $(PWD)/test_wokwi.v
else