template files and paths

This commit is contained in:
matt venn
2023-03-16 15:41:54 +01:00
parent 9e6891f111
commit b5745ccf4d
9 changed files with 8581 additions and 24 deletions
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RBA::Application.instance.main_window.current_view.save_image("./tinytapeout.png",2000,2000)
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<?xml version="1.0" encoding="utf-8"?>
<config>
<absolute-units>false</absolute-units>
<abstract-mode-enabled>false</abstract-mode-enabled>
<abstract-mode-width>10.0</abstract-mode-width>
<apply-text-trans>true</apply-text-trans>
<background-color>auto</background-color>
<bitmap-caching>true</bitmap-caching>
<bitmap-oversampling>1</bitmap-oversampling>
<cell-list-sorting>by-name</cell-list-sorting>
<child-context-color>auto</child-context-color>
<child-context-dimming>50</child-context-dimming>
<child-context-enabled>false</child-context-enabled>
<child-context-hollow>false</child-context-hollow>
<cib-context-cell/>
<cib-context-mode>any-top</cib-context-mode>
<cib-max-inst-count>1000</cib-max-inst-count>
<cib-window-dim>1.0</cib-window-dim>
<cib-window-mode>fit-marker</cib-window-mode>
<cib-window-state/>
<circle-points>32</circle-points>
<clear-ruler-new-cell>false</clear-ruler-new-cell>
<color-palette/>
<combine-mode>add</combine-mode>
<context-color>auto</context-color>
<context-dimming>50</context-dimming>
<context-hollow>false</context-hollow>
<current-lib-view/>
<current-ruler-template>0</current-ruler-template>
<custom-macro-paths/>
<dbu-units>false</dbu-units>
<def-import-spec/>
<default-add-other-layers>false</default-add-other-layers>
<default-font-size>0</default-font-size>
<default-grids>0.01,0.005,0.001</default-grids>
<default-layer-properties/>
<default-text-size>0.1</default-text-size>
<diff-detailed>false</diff-detailed>
<diff-exact>false</diff-exact>
<diff-expand-cell-arrays>false</diff-expand-cell-arrays>
<diff-run-xor>false</diff-run-xor>
<diff-summarize>false</diff-summarize>
<digits-dbu>2</digits-dbu>
<digits-micron>5</digits-micron>
<draw-array-border-instances>false</draw-array-border-instances>
<drawing-workers>1</drawing-workers>
<drop-small-cells>false</drop-small-cells>
<drop-small-cells-condition>0</drop-small-cells-condition>
<drop-small-cells-value>10</drop-small-cells-value>
<edit-connect-angle-mode>any</edit-connect-angle-mode>
<edit-grid>global</edit-grid>
<edit-hier-copy-mode>-1</edit-hier-copy-mode>
<edit-inst-angle>0</edit-inst-angle>
<edit-inst-array>false</edit-inst-array>
<edit-inst-cell-name/>
<edit-inst-column_x>0</edit-inst-column_x>
<edit-inst-column_y>0</edit-inst-column_y>
<edit-inst-columns>1</edit-inst-columns>
<edit-inst-lib-name/>
<edit-inst-mirror>false</edit-inst-mirror>
<edit-inst-pcell-parameters/>
<edit-inst-place-origin>false</edit-inst-place-origin>
<edit-inst-row_x>0</edit-inst-row_x>
<edit-inst-row_y>0</edit-inst-row_y>
<edit-inst-rows>1</edit-inst-rows>
<edit-inst-scale>1</edit-inst-scale>
<edit-max-shapes-of-instances>1000</edit-max-shapes-of-instances>
<edit-mode>false</edit-mode>
<edit-move-angle-mode>any</edit-move-angle-mode>
<edit-path-ext-type>flush</edit-path-ext-type>
<edit-path-ext-var-begin>0.0</edit-path-ext-var-begin>
<edit-path-ext-var-end>0.0</edit-path-ext-var-end>
<edit-path-width>0.1</edit-path-width>
<edit-show-shapes-of-instances>true</edit-show-shapes-of-instances>
<edit-snap-to-objects>false</edit-snap-to-objects>
<edit-text-halign>left</edit-text-halign>
<edit-text-size>0</edit-text-size>
<edit-text-string>ABC</edit-text-string>
<edit-text-valign>bottom</edit-text-valign>
<edit-top-level-selection>false</edit-top-level-selection>
<fit-new-cell>true</fit-new-cell>
<flat-cell-list>false</flat-cell-list>
<full-hierarchy-new-cell>true</full-hierarchy-new-cell>
<global-trans>r0</global-trans>
<grid-axis-color>auto</grid-axis-color>
<grid-color>auto</grid-color>
<grid-grid-color>auto</grid-grid-color>
<grid-micron>0.001</grid-micron>
<grid-ruler-color>auto</grid-ruler-color>
<grid-show-ruler>true</grid-show-ruler>
<grid-style0>invisible</grid-style0>
<grid-style1>dots</grid-style1>
<grid-style2>tenths-dotted-lines</grid-style2>
<grid-visible>true</grid-visible>
<guiding-shape-color>auto</guiding-shape-color>
<guiding-shape-line-width>1</guiding-shape-line-width>
<guiding-shape-vertex-size>5</guiding-shape-vertex-size>
<guiding-shape-visible>true</guiding-shape-visible>
<hide-empty-layers>false</hide-empty-layers>
<image-cache-size>1</image-cache-size>
<initial-hier-depth>1</initial-hier-depth>
<initial-technology/>
<inst-color>auto</inst-color>
<inst-label-font>0</inst-label-font>
<inst-label-transform>true</inst-label-transform>
<inst-visible>true</inst-visible>
<key-bindings/>
<l2ndb-export-circuit-cell-prefix>CIRCUIT_</l2ndb-export-circuit-cell-prefix>
<l2ndb-export-device-cell-prefix>DEVICE_</l2ndb-export-device-cell-prefix>
<l2ndb-export-net-cell-prefix>NET_</l2ndb-export-net-cell-prefix>
<l2ndb-export-net-propname/>
<l2ndb-export-produce-circuit-cells>false</l2ndb-export-produce-circuit-cells>
<l2ndb-export-produce-device-cells>false</l2ndb-export-produce-device-cells>
<l2ndb-export-start-layer-number>1000</l2ndb-export-start-layer-number>
<l2ndb-marker-color>auto</l2ndb-marker-color>
<l2ndb-marker-cycle-colors>255,0,0 0,255,0 0,0,255 255,255,0 255,0,255 0,255,255 160,80,255 255,160,0</l2ndb-marker-cycle-colors>
<l2ndb-marker-cycle-colors-enabled>false</l2ndb-marker-cycle-colors-enabled>
<l2ndb-marker-dither-pattern>-1</l2ndb-marker-dither-pattern>
<l2ndb-marker-halo>-1</l2ndb-marker-halo>
<l2ndb-marker-intensity>50</l2ndb-marker-intensity>
<l2ndb-marker-line-width>-1</l2ndb-marker-line-width>
<l2ndb-marker-use-original-colors>false</l2ndb-marker-use-original-colors>
<l2ndb-marker-vertex-size>-1</l2ndb-marker-vertex-size>
<l2ndb-max-shapes-highlighted>10000</l2ndb-max-shapes-highlighted>
<l2ndb-show-all>true</l2ndb-show-all>
<l2ndb-window-dim>1.0</l2ndb-window-dim>
<l2ndb-window-mode>fit-net</l2ndb-window-mode>
<l2ndb-window-state/>
<layers-always-show-layout-index>false</layers-always-show-layout-index>
<layers-always-show-ld>true</layers-always-show-ld>
<layers-always-show-source>false</layers-always-show-source>
<layout-file-watcher-enabled>true</layout-file-watcher-enabled>
<lef-import-spec/>
<line-style-palette/>
<macro-editor-active-macro/>
<macro-editor-console-interpreter/>
<macro-editor-console-mru/>
<macro-editor-current-macro/>
<macro-editor-debugging-enabled>true</macro-editor-debugging-enabled>
<macro-editor-file-watcher-enabled>true</macro-editor-file-watcher-enabled>
<macro-editor-font-family/>
<macro-editor-font-size/>
<macro-editor-indent>2</macro-editor-indent>
<macro-editor-open-macros/>
<macro-editor-save-all-on-run>false</macro-editor-save-all-on-run>
<macro-editor-stop-on-exception>true</macro-editor-stop-on-exception>
<macro-editor-styles/>
<macro-editor-tab-width>8</macro-editor-tab-width>
<macro-editor-watch-expressions/>
<macro-editor-window-state/>
<markers-visible>true</markers-visible>
<menu-items-hidden/>
<min-inst-label-size>16</min-inst-label-size>
<mouse-wheel-mode>0</mouse-wheel-mode>
<mru>'/home/matt/work/asic-workshop/shuttle6/zero_to_asic_mpw6/gds/user_project_wrapper.gds.gz' '/home/matt/work/asic-workshop/shuttle7/zero_to_asic_mpw7/gds/user_project_wrapper.gds.gz' '/home/matt/work/asic-workshop/shuttle7/tinytapeout-02/gds/user_project_wrapper.gds' '/home/matt/work/asic-workshop/shuttle8/tinytapeout-02/gds/user_project_wrapper.gds' '/home/matt/work/asic-workshop/shuttle9/caravel_user_project/gds/user_project_wrapper.gds'</mru>
<navigator-show-all-hier-levels>false</navigator-show-all-hier-levels>
<navigator-show-images>true</navigator-show-images>
<no-stipple>false</no-stipple>
<nt-marker-color>auto</nt-marker-color>
<nt-marker-cycle-colors>255,0,0 0,255,0 0,0,255 255,255,0 255,0,255 0,255,255 160,80,255 255,160,0</nt-marker-cycle-colors>
<nt-marker-cycle-colors-enabled>false</nt-marker-cycle-colors-enabled>
<nt-marker-dither-pattern>-1</nt-marker-dither-pattern>
<nt-marker-halo>-1</nt-marker-halo>
<nt-marker-intensity>50</nt-marker-intensity>
<nt-marker-line-width>-1</nt-marker-line-width>
<nt-marker-vertex-size>-1</nt-marker-vertex-size>
<nt-max-shapes-highlighted>10000</nt-max-shapes-highlighted>
<nt-window-dim>1.0</nt-window-dim>
<nt-window-mode>fit-net</nt-window-mode>
<pan-distance>0.15</pan-distance>
<paste-display-mode>2</paste-display-mode>
<pcb-import-spec/>
<rdb-context-mode>database-top</rdb-context-mode>
<rdb-marker-color>auto</rdb-marker-color>
<rdb-marker-dither-pattern>-1</rdb-marker-dither-pattern>
<rdb-marker-halo>-1</rdb-marker-halo>
<rdb-marker-line-width>-1</rdb-marker-line-width>
<rdb-marker-vertex-size>-1</rdb-marker-vertex-size>
<rdb-max-marker-count>1000</rdb-max-marker-count>
<rdb-window-dim>1.0</rdb-window-dim>
<rdb-window-mode>fit-marker</rdb-window-mode>
<rdb-window-state-v2/>
<reader-options-show-always>false</reader-options-show-always>
<ruler-color>auto</ruler-color>
<ruler-grid-snap>false</ruler-grid-snap>
<ruler-halo>true</ruler-halo>
<ruler-obj-snap>true</ruler-obj-snap>
<ruler-snap-mode>any</ruler-snap-mode>
<ruler-snap-range>8</ruler-snap-range>
<ruler-templates>mode=normal,title=Ruler,category=_ruler,fmt=$D,fmt_x=$X,fmt_y=$Y,position=auto,xalign=auto,yalign=auto,xlabel_xalign=auto,xlabel_yalign=auto,ylabel_xalign=auto,ylabel_yalign=auto,style=ruler,outline=diag,snap=true,angle_constraint=global;mode=single_click,title=Cross,category=_cross,fmt='$U,$V',fmt_x='',fmt_y='',position=auto,xalign=auto,yalign=auto,xlabel_xalign=auto,xlabel_yalign=auto,ylabel_xalign=auto,ylabel_yalign=auto,style=cross_both,outline=diag,snap=true,angle_constraint=global;mode=auto_metric,title=Measure,category=_measure,fmt=$D,fmt_x=$X,fmt_y=$Y,position=auto,xalign=auto,yalign=auto,xlabel_xalign=auto,xlabel_yalign=auto,ylabel_xalign=auto,ylabel_yalign=auto,style=ruler,outline=diag,snap=true,angle_constraint=global;mode=normal,title=Ellipse,category='',fmt='',fmt_x='W=$(abs(X))',fmt_y='H=$(abs(Y))',position=auto,xalign=auto,yalign=auto,xlabel_xalign=auto,xlabel_yalign=auto,ylabel_xalign=auto,ylabel_yalign=auto,style=line,outline=ellipse,snap=true,angle_constraint=global;mode=normal,title=Box,category='',fmt='',fmt_x='W=$(abs(X))',fmt_y='H=$(abs(Y))',position=auto,xalign=auto,yalign=auto,xlabel_xalign=auto,xlabel_yalign=auto,ylabel_xalign=auto,ylabel_yalign=auto,style=line,outline=box,snap=true,angle_constraint=global;mode=normal,title=XSection,category=XS,fmt=XS,fmt_x='',fmt_y='',position=auto,xalign=auto,yalign=auto,xlabel_xalign=auto,xlabel_yalign=auto,ylabel_xalign=auto,ylabel_yalign=auto,style=arrow_both,outline=diag,snap=true,angle_constraint=global</ruler-templates>
<rulers>-1</rulers>
<salt-manager-window-state/>
<search-range>5</search-range>
<sel-color>auto</sel-color>
<sel-dither-pattern>1</sel-dither-pattern>
<sel-halo>true</sel-halo>
<sel-inside-pcells-mode>false</sel-inside-pcells-mode>
<sel-line-width>1</sel-line-width>
<sel-transient-mode>true</sel-transient-mode>
<sel-vertex-size>3</sel-vertex-size>
<shb-context-cell/>
<shb-context-mode>any-top</shb-context-mode>
<shb-max-inst-count>1000</shb-max-inst-count>
<shb-max-shape-count>1000</shb-max-shape-count>
<shb-window-dim>1.0</shb-window-dim>
<shb-window-mode>fit-marker</shb-window-mode>
<shb-window-state/>
<show-bookmarks-view>false</show-bookmarks-view>
<show-hierarchy-panel>true</show-hierarchy-panel>
<show-layer-panel>true</show-layer-panel>
<show-layer-toolbox>true</show-layer-toolbox>
<show-libraries-view>true</show-libraries-view>
<show-navigator>false</show-navigator>
<show-properties>false</show-properties>
<show-toolbar>true</show-toolbar>
<split-cell-list>false</split-cell-list>
<split-lib-views>false</split-lib-views>
<sr-max-item-count>1000</sr-max-item-count>
<sr-window-dim>1.0</sr-window-dim>
<sr-window-mode>fit-marker</sr-window-mode>
<sr-window-state/>
<stipple-offset>true</stipple-offset>
<stipple-palette/>
<stream-import-spec2/>
<synchronized-views>false</synchronized-views>
<tech-editor-window-state/>
<technology-data/>
<test-shapes-in-view>false</test-shapes-in-view>
<text-color>auto</text-color>
<text-font>0</text-font>
<text-lazy-rendering>true</text-lazy-rendering>
<text-visible>true</text-visible>
<tip-window-hidden>editor-mode=4,editor-mode=0</tip-window-hidden>
<window-geometry/>
<window-state/>
<xor-anotb>false</xor-anotb>
<xor-axorb>true</xor-axorb>
<xor-bnota>false</xor-bnota>
<xor-input-mode>all</xor-input-mode>
<xor-layer-offset/>
<xor-num-workers>1</xor-num-workers>
<xor-output-mode>rdb</xor-output-mode>
<xor-region-mode>all</xor-region-mode>
<xor-summarize>false</xor-summarize>
<xor-tiling/>
<xor-tolerances/>
</config>
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{
"DESIGN_NAME": "user_project_wrapper",
"VERILOG_FILES": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/rtl/user_project_wrapper.v"
],
"ROUTING_CORES": 8,
"CLOCK_PERIOD": 25,
"CLOCK_PORT": "wb_clk_i",
"CLOCK_NET": "mprj.clk",
"FP_PDN_MACRO_HOOKS": [],
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
"PDN_CFG": "dir::pdn_cfg.tcl",
"MAGIC_DEF_LABELS": 0,
"VERILOG_FILES_BLACKBOX": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/blackbox_project_includes.v"
],
"EXTRA_LEFS": [],
"EXTRA_GDS_FILES": [],
"BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
"RUN_KLAYOUT_XOR": 0,
"RUN_KLAYOUT_DRC": 0,
"RUN_MAGIC_DRC": 0,
"IO_SYNC": 0,
"FP_PDN_CHECK_NODES": 0,
"SYNTH_ELABORATE_ONLY": 1,
"PL_RANDOM_GLB_PLACEMENT": 1,
"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
"FP_PDN_ENABLE_RAILS": 0,
"DIODE_INSERTION_STRATEGY": 0,
"RUN_FILL_INSERTION": 0,
"RUN_TAP_DECAP_INSERTION": 0,
"FP_PDN_VPITCH": 140,
"FP_PDN_VOFFSET": 186,
"FP_PDN_HPITCH": 185,
"FP_PDN_HOFFSET": 130,
"CLOCK_TREE_SYNTH": 0,
"MAGIC_ZEROIZE_ORIGIN": 0,
"FP_SIZING": "absolute",
"RUN_CVC": 0,
"UNIT": 2.4,
"FP_IO_VEXTEND": "expr::2 * $UNIT",
"FP_IO_HEXTEND": "expr::2 * $UNIT",
"FP_IO_VLENGTH": "expr::$UNIT",
"FP_IO_HLENGTH": "expr::$UNIT",
"FP_IO_VTHICKNESS_MULT": 4,
"FP_IO_HTHICKNESS_MULT": 4,
"FP_PDN_CORE_RING": 1,
"FP_PDN_CORE_RING_VWIDTH": 3.1,
"FP_PDN_CORE_RING_HWIDTH": 3.1,
"FP_PDN_CORE_RING_VOFFSET": 12.45,
"FP_PDN_CORE_RING_HOFFSET": 12.45,
"FP_PDN_CORE_RING_VSPACING": 1.7,
"FP_PDN_CORE_RING_HSPACING": 1.7,
"FP_PDN_VWIDTH": 3.1,
"FP_PDN_HWIDTH": 3.1,
"FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
"FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
"VDD_NETS": [
"vccd1",
"vccd2",
"vdda1",
"vdda2"
],
"GND_NETS": [
"vssd1",
"vssd2",
"vssa1",
"vssa2"
],
"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
"pdk::sky130*": {
"RT_MAX_LAYER": "met4",
"DIE_AREA": "0 0 2920 3520",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
"scl::sky130_fd_sc_hd": {
"CLOCK_PERIOD": 25
},
"scl::sky130_fd_sc_hdll": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
"CLOCK_PERIOD": 10,
"SYNTH_MAX_FANOUT": 5
},
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
},
"pdk::gf180mcuC": {
"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
"FP_PDN_CHECK_NODES": 0,
"FP_PDN_ENABLE_RAILS": 0,
"RT_MAX_LAYER": "Metal4",
"DIE_AREA": "0 0 3000 3000",
"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
"PL_OPENPHYSYN_OPTIMIZATIONS": 0,
"DIODE_INSERTION_STRATEGY": 0,
"MAGIC_WRITE_FULL_LEF": 0
}
}
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// end of module instantiation
endmodule // user_project_wrapper
`default_nettype wire
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_project_wrapper
*
* This wrapper enumerates all of the pins available to the
* user for the user project.
*
* An example user project is provided in this wrapper. The
* example should be removed and replaced with the actual
* user project.
*
* THIS FILE HAS BEEN GENERATED USING multi_tools_project CODEGEN
* IF YOU NEED TO MAKE EDITS TO IT, EDIT codegen/caravel_iface_header.txt
*
*-------------------------------------------------------------
*/
module user_project_wrapper #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,
// Independent clock (on independent integer divider)
input user_clock2,
// User maskable interrupt signals
output [2:0] user_irq
);
// start of module instantiation