TinyTapeout/tt-support-tools
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Merge branch 'tt05' of https://github.com/TinyTapeout/tt-support-tools into tt05

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Matt Venn
2023-09-11 15:33:25 +02:00
parent 37c18a964e 23da39ba14
commit b5e5bc99e8
3 changed files with 7 additions and 13 deletions
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configure.py
+1 -3
View File
@@ -27,7 +27,7 @@ class Projects():
self.projects = [] self.projects = []
project_list = [entry for entry in os.listdir(self.project_dir) if os.path.isdir(os.path.join(self.project_dir, entry))] project_list = [entry for entry in os.listdir(self.project_dir) if os.path.isdir(os.path.join(self.project_dir, entry))]
if args.test: if args.test:
project_list = ['tt_um_factory_test'] project_list = ['tt_um_chip_rom', 'tt_um_factory_test']
elif args.sta_projects: elif args.sta_projects:
project_list = ['tt_um_loopback'] project_list = ['tt_um_loopback']
@@ -242,8 +242,6 @@ if __name__ == '__main__':
if args.update_shuttle: if args.update_shuttle:
shuttle.configure_mux() shuttle.configure_mux()
if args.test:
shuttle.write_gl_config()
rom.write_rom() rom.write_rom()
if not args.test: if not args.test:
docs.build_index() docs.build_index()
rom/tt_um_chip_rom.v
+5 -1
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@@ -8,6 +8,10 @@
`default_nettype none `default_nettype none
`ifndef ROM_VMEM_PATH
`define ROM_VMEM_PATH "rom.vmem"
`endif
module tt_um_chip_rom ( module tt_um_chip_rom (
input wire [7:0] ui_in, // Dedicated inputs input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs output wire [7:0] uo_out, // Dedicated outputs
@@ -22,7 +26,7 @@ module tt_um_chip_rom (
reg [7:0] rom_data [0:255]; reg [7:0] rom_data [0:255];
initial begin initial begin
$readmemh("rom.vmem", rom_data); $readmemh(`ROM_VMEM_PATH, rom_data);
end end
assign uo_out = rom_data[ui_in]; assign uo_out = rom_data[ui_in];
shuttle.py
+1 -9
View File
@@ -25,14 +25,6 @@ class ShuttleConfig():
self.script_dir = os.path.dirname(os.path.realpath(__file__)) self.script_dir = os.path.dirname(os.path.realpath(__file__))
self.modules_yaml_name = modules_yaml_name self.modules_yaml_name = modules_yaml_name
def write_gl_config(self):
with open('verilog/includes/includes.gl.caravel_user_project', 'w') as fh:
fh.write('-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v\n')
fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_ctrl.v\n')
fh.write('-v $(USER_PROJECT_VERILOG)/gl/tt_mux.v\n')
for project in self.projects:
fh.write(f'-v $(USER_PROJECT_VERILOG)/../projects/{project.top_module}/{project.get_gl_verilog_filename()}\n')
def configure_mux(self): def configure_mux(self):
with open(self.modules_yaml_name, 'r') as modules_file: with open(self.modules_yaml_name, 'r') as modules_file:
module_config = yaml.safe_load(modules_file) module_config = yaml.safe_load(modules_file)
@@ -127,7 +119,7 @@ class ShuttleConfig():
def copy_final_results(self): def copy_final_results(self):
macros = ["tt_ctrl", "tt_mux", "tt_top"] macros = ["tt_um_chip_rom", "tt_ctrl", "tt_mux", "tt_top"]
logging.info('copying final results:') logging.info('copying final results:')
for macro in macros: for macro in macros: