feat(fpga): initial implementation

Adds a new `tt_tool.py --create-fpga-bitstream` flag that creates a TT Sim FPGA bitstream from the user's project.

fpga/tt_fpga_top.pcf

@@ -0,0 +1,68 @@
+#
+# Pinmap for the TT ASIC SIMULATOR version 1.0
+#
+
+
+# Clock
+set_io -nowarn clk_fpga 37 # IOT_45a_G1
+
+
+# SPI
+set_io -nowarn spi_mosi 14
+set_io -nowarn spi_miso 17
+set_io -nowarn spi_clk  15
+set_io -nowarn spi_cs_n 16
+
+# USB
+set_io -nowarn usb_dp 32 # IOT_43A
+set_io -nowarn usb_dn 31 # IOT_42B
+set_io -nowarn usb_pu 34 # IOT_44B 
+
+
+# Button
+set_io -nowarn -pullup yes btn 13 # IOB_24A / boot button
+
+
+# Leds
+set_io -nowarn rgb[0] 39
+set_io -nowarn rgb[1] 40
+set_io -nowarn rgb[2] 41
+
+
+# "project clock"
+set_io -nowarn  clk   35 # IOT_46B_G0
+set_io -nowarn  rst_n   38 # IOT_50B
+set_io -nowarn  gpio_led      36 # IOT_48B
+
+
+# I/O
+# pmod buttons
+set_io -nowarn ui_in[0]       2
+set_io -nowarn ui_in[1]       3
+set_io -nowarn ui_in[2]       4
+set_io -nowarn ui_in[3]       6
+set_io -nowarn ui_in[4]       9
+set_io -nowarn ui_in[5]       10
+set_io -nowarn ui_in[6]       11
+set_io -nowarn ui_in[7]       12
+
+
+set_io -nowarn uo_out[0]      18 
+set_io -nowarn uo_out[1]      20
+set_io -nowarn uo_out[2]      19
+set_io -nowarn uo_out[3]      21
+set_io -nowarn uo_out[4]      23
+set_io -nowarn uo_out[5]      26
+set_io -nowarn uo_out[6]      25
+set_io -nowarn uo_out[7]      28
+     
+
+
+set_io -nowarn uio[0]        27     
+set_io -nowarn uio[1]        42
+set_io -nowarn uio[2]        44
+set_io -nowarn uio[3]        43
+set_io -nowarn uio[4]        46
+set_io -nowarn uio[5]        45
+set_io -nowarn uio[6]        48
+set_io -nowarn uio[7]        47

fpga/tt_fpga_top.v

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: Apache 2.0
+// Copyright (C) 2024, Tiny Tapeout LTD
+
+`default_nettype none
+
+module tt_fpga_top (
+    input  wire [7:0] ui_in,
+    output wire [7:0] uo_out,
+    inout  wire [7:0] uio,
+    input  wire       clk,
+    input  wire       rst_n
+);
+  wire [7:0] uio_in;
+  wire [7:0] uio_out;
+  wire [7:0] uio_oe;
+
+  SB_IO #(
+      .PIN_TYPE(6'b1010_01)
+  ) uio_pin[7:0] (
+      .PACKAGE_PIN(uio),
+      .OUTPUT_ENABLE(uio_oe),
+      .D_OUT_0(uio_out),
+      .D_IN_0(uio_in),
+  );
+
+  __tt_um_placeholder user_project (
+      .ui_in(ui_in),
+      .uo_out(uo_out),
+      .uio_in(uio_in),
+      .uio_out(uio_out),
+      .uio_oe(uio_oe),
+      .ena(1'b1),
+      .clk(clk),
+      .rst_n(rst_n)
+  );
+
+endmodule