feat: Chip ROM auto generation with OpenLane 2

So we can generate the ROM while building the shuttle's GDS

rom/.gitignore

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+runs
+rom.vmem

rom/config.json

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+{
+  "DESIGN_NAME": "tt_um_chip_rom",
+  "VERILOG_FILES": "dir::tt_um_chip_rom.v",
+  
+  "FP_SIZING": "absolute",
+  "DIE_AREA": "0 0 168.36 111.52",
+  "FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../def/tt_block_1x1.def",
+
+  "FP_IO_HLENGTH": 2,
+  "FP_IO_VLENGTH": 2,
+
+  "//": "use alternative efabless decap cells to solve LI density issue",
+  "DECAP_CELL": "sky130_fd_sc_hd__decap_3 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_8 sky130_ef_sc_hd__decap_12",
+
+  "//": "period is in ns, so 20ns == 50mHz",
+  "CLOCK_PERIOD": 20,
+  "CLOCK_PORT": "clk",
+
+  "//": "don't use power rings or met5",
+  "DESIGN_IS_CORE": false,
+  "RT_MAX_LAYER": "met4",
+
+  "//": "save some time",
+  "RUN_KLAYOUT_XOR": false,
+
+  "//": "reduce wasted space",
+  "TOP_MARGIN_MULT": 1,
+  "BOTTOM_MARGIN_MULT": 1,
+  "LEFT_MARGIN_MULT": 6,
+  "RIGHT_MARGIN_MULT": 6
+}

rom/tt_um_chip_rom.v

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+/*
+ * tt_um_chip_rom.v
+ *
+ * ROM module for Tiny Tapeout chips
+ *
+ * Author: Uri Shaked
+ */
+
+`default_nettype none
+
+module tt_um_chip_rom (
+	input  wire [7:0] ui_in,	// Dedicated inputs
+	output wire [7:0] uo_out,	// Dedicated outputs
+	input  wire [7:0] uio_in,	// IOs: Input path
+	output wire [7:0] uio_out,// IOs: Output path
+	output wire [7:0] uio_oe,	// IOs: Enable path (active high: 0=input, 1=output)
+	input  wire       ena,
+	input  wire       clk,
+	input  wire       rst_n
+);
+
+	reg [7:0] rom_data [0:255];
+
+  initial begin
+		$readmemh("rom.vmem", rom_data);
+	end
+	
+	assign uo_out  = rom_data[ui_in];
+	assign uio_out = 8'h00;
+	assign uio_oe  = 8'h00;
+
+endmodule // tt_um_chip_rom