From cfa06bae536d00282cb2fdb3d0bdeebc562c6365 Mon Sep 17 00:00:00 2001
From: William Zhang <108840645+WilliamZhang20@users.noreply.github.com>
Date: Thu, 17 Sep 2026 14:16:53 -0400
Subject: [PATCH] fix(precheck): allow SRAM and DigiBnd layers in SG13CMOS5L
 precheck (#187)

---
 precheck/tech_data.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/precheck/tech_data.py b/precheck/tech_data.py
index dc21f3a..f42a2d3 100644
--- a/precheck/tech_data.py
+++ b/precheck/tech_data.py
@@ -66,7 +66,7 @@ valid_layers_ihp_sg13cmos5l = [
     "Metal3.label", "Metal3.nofill", "Metal3.pin", "Metal3.slit", "Metal3.text", "Metal3.res", "Via3.drawing",
     "Metal4.drawing", "Metal4.label", "Metal4.nofill", "Metal4.pin", "Metal4.slit", "Metal4.text", "Metal4.res",
     "TopMetal1.nofill", "TEXT.drawing", "Recog.drawing", "Recog.pin", "Recog.esd", "Recog.diode", "Recog.tsv",
-    "Recog.pdiode", "Recog.mom", "RES.drawing", "RES.label", "HeatRes.drawing", "EXTBlock.drawing", "prBoundary.drawing",
+    "Recog.pdiode", "Recog.mom", "RES.drawing", "RES.label", "SRAM.drawing", "DigiBnd.drawing", "HeatRes.drawing", "EXTBlock.drawing", "prBoundary.drawing",
     "prBoundary.label", "prBoundary.boundary",
 ]