From d026569b28bde5d04ef78b921310c516c5546bac Mon Sep 17 00:00:00 2001 From: Uri Shaked Date: Fri, 5 Jul 2024 10:44:49 +0300 Subject: [PATCH] feat(tt_tool): experimental micro tiles support --- def/tt_block_micro.def | 136 +++++++++++++++++++++++++++++++++++++++++ precheck/precheck.py | 5 +- project.py | 10 ++- tile_sizes.yaml | 1 + 4 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 def/tt_block_micro.def diff --git a/def/tt_block_micro.def b/def/tt_block_micro.def new file mode 100644 index 0000000..b8a2262 --- /dev/null +++ b/def/tt_block_micro.def @@ -0,0 +1,136 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 65000 50000 ) ; +ROW ROW_0 unithd 2760 2720 N DO 71 BY 1 STEP 460 0 ; +ROW ROW_1 unithd 2760 5440 FS DO 71 BY 1 STEP 460 0 ; +ROW ROW_2 unithd 2760 8160 N DO 71 BY 1 STEP 460 0 ; +ROW ROW_3 unithd 2760 10880 FS DO 71 BY 1 STEP 460 0 ; +ROW ROW_4 unithd 2760 13600 N DO 71 BY 1 STEP 460 0 ; +ROW ROW_5 unithd 2760 16320 FS DO 71 BY 1 STEP 460 0 ; +ROW ROW_6 unithd 2760 19040 N DO 71 BY 1 STEP 460 0 ; +ROW ROW_7 unithd 2760 21760 FS DO 71 BY 1 STEP 460 0 ; +ROW ROW_8 unithd 2760 24480 N DO 71 BY 1 STEP 460 0 ; +ROW ROW_9 unithd 2760 27200 FS DO 71 BY 1 STEP 460 0 ; +ROW ROW_10 unithd 2760 29920 N DO 71 BY 1 STEP 460 0 ; +ROW ROW_11 unithd 2760 32640 FS DO 71 BY 1 STEP 460 0 ; +ROW ROW_12 unithd 2760 35360 N DO 71 BY 1 STEP 460 0 ; +ROW ROW_13 unithd 2760 38080 FS DO 71 BY 1 STEP 460 0 ; +ROW ROW_14 unithd 2760 40800 N DO 71 BY 1 STEP 460 0 ; +ROW ROW_15 unithd 2760 43520 FS DO 71 BY 1 STEP 460 0 ; +ROW ROW_16 unithd 2760 46240 N DO 71 BY 1 STEP 460 0 ; +TRACKS X 230 DO 350 STEP 460 LAYER li1 ; +TRACKS Y 170 DO 328 STEP 340 LAYER li1 ; +TRACKS X 170 DO 473 STEP 340 LAYER met1 ; +TRACKS Y 170 DO 328 STEP 340 LAYER met1 ; +TRACKS X 230 DO 350 STEP 460 LAYER met2 ; +TRACKS Y 230 DO 242 STEP 460 LAYER met2 ; +TRACKS X 340 DO 237 STEP 680 LAYER met3 ; +TRACKS Y 340 DO 164 STEP 680 LAYER met3 ; +TRACKS X 460 DO 175 STEP 920 LAYER met4 ; +TRACKS Y 460 DO 121 STEP 920 LAYER met4 ; +TRACKS X 1700 DO 47 STEP 3400 LAYER met5 ; +TRACKS Y 1700 DO 33 STEP 3400 LAYER met5 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 18 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64000 49500 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60320 49500 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 49500 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52960 49500 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 49280 49500 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45600 49500 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41920 49500 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 38240 49500 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 34560 49500 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 30880 49500 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 27200 49500 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 23520 49500 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 19840 49500 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 16160 49500 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 12480 49500 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 8800 49500 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 5120 49500 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met4 ( -150 -500 ) ( 150 500 ) + + PLACED ( 1440 49500 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 18 ; + - clk ( PIN clk ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/precheck/precheck.py b/precheck/precheck.py index e93b5d6..b5bc4be 100644 --- a/precheck/precheck.py +++ b/precheck/precheck.py @@ -171,7 +171,10 @@ def main(): else: template_def = f"../def/analog/tt_analog_{tiles}.def" else: - template_def = f"../def/tt_block_{tiles}_pg.def" + if tiles == "micro": + template_def = f"../def/tt_block_{tiles}.def" + else: + template_def = f"../def/tt_block_{tiles}_pg.def" logging.info(f"using def template {template_def}") checks = [ diff --git a/project.py b/project.py index 913eb32..f59606d 100644 --- a/project.py +++ b/project.py @@ -214,6 +214,13 @@ class Project: required_ports += [ ["inout", "ua", 8], ] + if self.info.tiles == "micro": + required_ports = [ + ["input", "clk", 1], + ["input", "rst_n", 1], + ["input", "ui_in", 8], + ["output", "uo_out", 8], + ] if include_power_ports: required_ports += [ ["input", "VGND", 1], @@ -469,11 +476,12 @@ class Project: logging.info("creating include file") tiles = self.info.tiles die_area = tile_sizes[tiles] + pg_suffix = "_pg" if tiles != "micro" else "" config = { "DESIGN_NAME": self.info.top_module, "VERILOG_FILES": [f"dir::{src}" for src in self.sources], "DIE_AREA": die_area, - "FP_DEF_TEMPLATE": f"dir::../tt/def/tt_block_{tiles}_pg.def", + "FP_DEF_TEMPLATE": f"dir::../tt/def/tt_block_{tiles}{pg_suffix}.def", } write_config(config, os.path.join(self.src_dir, "user_config"), ("json",)) diff --git a/tile_sizes.yaml b/tile_sizes.yaml index d87541b..c0a23b5 100644 --- a/tile_sizes.yaml +++ b/tile_sizes.yaml @@ -1,3 +1,4 @@ +micro: "0 0 65.00 50.00" 1x1: "0 0 161.00 111.52" 1x2: "0 0 161.00 225.76" 2x2: "0 0 334.88 225.76"