TinyTapeout/tt-support-tools
1
0
Fork 0
mirror of https://github.com/TinyTapeout/tt-support-tools.git synced 2026-11-03 04:36:09 +01:00
Code Issues Packages Projects Releases Wiki Activity

fix(configure): support declaring power ports as inout

Browse Source 
OpenLane 2.1.1 produces a verilog netlist with the power ports declared as "inout", where as 2.0.8 and earlier declared the power ports as "input". Change our scripts to accept "inout" as a valid direction for the power ports.
This commit is contained in:
Uri Shaked
2024-08-30 11:39:52 +03:00
parent 86beb5d8ec
commit d3ed62bc00
1 changed files with 10 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
project.py
+10 -6
View File
@@ -23,9 +23,11 @@ from project_info import ProjectInfo, ProjectYamlError
_CELL_URL_FMT = "https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/cells/{name}/README.html" _CELL_URL_FMT = "https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/cells/{name}/README.html"
def _cell_url(cell_name): def _cell_url(cell_name):
return _CELL_URL_FMT.format(name=cell_name) return _CELL_URL_FMT.format(name=cell_name)
PINOUT_KEYS = [ PINOUT_KEYS = [
"ui[0]", "ui[0]",
"ui[1]", "ui[1]",
@@ -219,21 +221,23 @@ class Project:
] ]
if include_power_ports: if include_power_ports:
required_ports += [ required_ports += [
["input", "VGND", 1], [("input", "inout"), "VGND", 1],
["input", "VDPWR", 1], [("input", "inout"), "VDPWR", 1],
] ]
if self.info.uses_3v3: if self.info.uses_3v3:
required_ports += [ required_ports += [
["input", "VAPWR", 1], [("input", "inout"), "VAPWR", 1],
] ]
for direction, port, bits in required_ports: for valid_directions, port, bits in required_ports:
if port not in module_ports: if port not in module_ports:
logging.error(f"{self} port '{port}' missing from top module ('{top}')") logging.error(f"{self} port '{port}' missing from top module ('{top}')")
exit(1) exit(1)
actual_direction = module_ports[port]["direction"] actual_direction = module_ports[port]["direction"]
if actual_direction != direction: if type(valid_directions) is str:
valid_directions = (valid_directions,)
if actual_direction not in valid_directions:
logging.error( logging.error(
f"{self} incorrect direction for port '{port}' in module '{top}': {direction} required, {actual_direction} found" f"{self} incorrect direction for port '{port}' in module '{top}': {valid_directions} required, {actual_direction} found"
) )
exit(1) exit(1)
actual_bits = len(module_ports[port]["bits"]) actual_bits = len(module_ports[port]["bits"])