mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
feat!: replace ihp-sg13g2 with ihp-sg13cmos5l
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@@ -2,7 +2,7 @@ import json
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import os
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from typing import Dict, List, Literal, Pattern, Protocol, Tuple, TypedDict, Union
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TechName = Literal["sky130A", "ihp-sg13g2", "gf180mcuD", "fpgaUp5k"]
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TechName = Literal["sky130A", "ihp-sg13cmos5l", "gf180mcuD", "fpgaUp5k"]
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class CellDefinition(TypedDict):
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@@ -128,16 +128,16 @@ class Sky130Tech(Tech):
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class IHPTech(Tech):
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is_fpga = False
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def_suffix = "pgvdd"
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librelane_pdk_args = "--pdk ihp-sg13g2"
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librelane_pdk_args = "--pdk ihp-sg13cmos5l --manual-pdk"
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tt_corner = "nom_typ_1p20V_25C"
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cell_regexp = r"^\s*sg13g2_(?P<cell_name>\S+)_(?P<cell_drive>\d+)"
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cell_regexp = r"^\s*sg13cmos5l_(?P<cell_name>\S+)_(?P<cell_drive>\d+)"
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netlist_type = "nl"
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project_top_metal_layer = "TopMetal1"
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project_top_metal_layer = "Metal4"
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librelane_config = {}
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label_layers = [
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(8, 1), # Metal1.label
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(8, 25), # Metal1.text
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(67, 25), # Metal5.text
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(50, 25), # Metal4.text
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(126, 25), # TopMetal1.text
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]
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buried_layers = [
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@@ -147,32 +147,32 @@ class IHPTech(Tech):
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(51, 0), # HeatTrans.drawing
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(189, 4), # prBoundary.boundary
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]
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scramble_cells = "sg13g2_"
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mux_config_yaml_name = "ihp-sg13g2.yaml"
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scramble_cells = "sg13cmos5l_"
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mux_config_yaml_name = "ihp-sg13cmos5l.yaml"
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mux_macros = [
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"pg/ihp-sg13g2/tt_pg_1v5_hp_1",
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"pg/ihp-sg13g2/tt_pg_1v5_hp_2",
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"pg/ihp-sg13g2/tt_pg_1v5_hp_4",
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"pg/ihp-sg13g2/tt_pg_1v5_ll_1",
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"pg/ihp-sg13g2/tt_pg_1v5_ll_2",
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"pg/ihp-sg13g2/tt_pg_1v5_ll_4",
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"pg/ihp-sg13cmos5l/tt_pg_1v5_hp_1",
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"pg/ihp-sg13cmos5l/tt_pg_1v5_hp_2",
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"pg/ihp-sg13cmos5l/tt_pg_1v5_hp_4",
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"pg/ihp-sg13cmos5l/tt_pg_1v5_ll_1",
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"pg/ihp-sg13cmos5l/tt_pg_1v5_ll_2",
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"pg/ihp-sg13cmos5l/tt_pg_1v5_ll_4",
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]
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extra_logo_macros = [
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"tech/ihp-sg13g2/tt_logo_corner",
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"tech/ihp-sg13cmos5l/tt_logo_corner",
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]
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prboundary_layer = (189, 4) # prBoundary.boundary
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logo_layer = (67, 0) # Metal5.drawing
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logo_layer_name = "Metal5"
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logo_layer = (50, 0) # Metal4.drawing
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logo_layer_name = "Metal4"
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logo_pixel_size = 0.25 # um
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def read_pdk_version(self, pdk_root: str) -> PDKVersionInfo:
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pdk_sources_file = os.path.join(pdk_root, "ihp-sg13g2", "SOURCES")
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pdk_sources_file = os.path.join(pdk_root, "ihp-sg13cmos5l", "SOURCES")
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return parse_openpdks_pdk_version(pdk_sources_file, "IHP-Open-PDK")
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def load_cell_definitions(self) -> Dict[str, CellDefinition]:
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URL_FORMAT = "https://raw.githubusercontent.com/IHP-GmbH/IHP-Open-PDK/refs/heads/main/ihp-sg13g2/libs.ref/sg13g2_stdcell/doc/sg13g2_stdcell_typ_1p20V_25C.pdf#{ref}"
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URL_FORMAT = "https://raw.githubusercontent.com/IHP-GmbH/IHP-Open-PDK/refs/heads/main/ihp-sg13cmos5l/libs.ref/sg13cmos5l_stdcell/doc/sg13cmos5l_stdcell_typ_1p20V_25C.pdf#{ref}"
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script_dir = os.path.dirname(os.path.realpath(__file__))
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with open(os.path.join(script_dir, "tech/ihp-sg13g2/cells.json")) as fh:
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with open(os.path.join(script_dir, "tech/ihp-sg13cmos5l/cells.json")) as fh:
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cells = json.load(fh)
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for cell in cells.values():
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cell["url"] = URL_FORMAT.format(ref=cell["doc_ref"])
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@@ -277,7 +277,7 @@ class FpgaTech(Tech):
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tech_map: dict[TechName, Tech] = {
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"ihp-sg13g2": IHPTech(),
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"ihp-sg13cmos5l": IHPTech(),
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"gf180mcuD": GF180MCUDTech(),
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"sky130A": Sky130Tech(),
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"fpgaUp5k": FpgaTech(),
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