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feat!: replace ihp-sg13g2 with ihp-sg13cmos5l

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This commit is contained in:
htfab
2026-03-15 17:22:51 +01:00
parent 24ea6a232a
commit db5da7076e
35 changed files with 74 additions and 129 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.github/workflows/test-harden.yaml
+8 -8
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@@ -10,7 +10,7 @@ jobs:
strategy:
fail-fast: false
matrix:
pdk: [sky130A, ihp-sg13g2, gf180mcuD]
pdk: [sky130A, ihp-sg13cmos5l, gf180mcuD]
runs-on: ubuntu-24.04
@@ -35,24 +35,24 @@ jobs:
run: pip install -r requirements.txt
- name: Install librelane
if: "${{ matrix.pdk != 'ihp-sg13g2' }}"
if: "${{ matrix.pdk != 'ihp-sg13cmos5l' }}"
run: pip install librelane==${LIBRELANE_VERSION}
# LibreLane 2.4.2 does not support ihp-sg13g2. Remove once 3.0.0 is released.
# LibreLane 2.4.2 does not support ihp-sg13cmos5l. Remove once 3.0.0 is released.
- name: Install librelane 3 dev (IHP only)
if: "${{ matrix.pdk == 'ihp-sg13g2' }}"
if: "${{ matrix.pdk == 'ihp-sg13cmos5l' }}"
run: pip install librelane==${LIBRELANE_VERSION_DEV}
- name: Clone the factory test
if: "${{ matrix.pdk != 'ihp-sg13g2' }}"
if: "${{ matrix.pdk != 'ihp-sg13cmos5l' }}"
run: git clone https://github.com/tinytapeout/ttsky25a-factory-test ${PROJECT_DIR}
- name: Clone the factory test (ihp-sg13g2)
if: "${{ matrix.pdk == 'ihp-sg13g2' }}"
- name: Clone the factory test (ihp-sg13cmos5l)
if: "${{ matrix.pdk == 'ihp-sg13cmos5l' }}"
run: git clone https://github.com/TinyTapeout/ttihp25b-factory-test ${PROJECT_DIR}
- name: Configure tt_tool.py args (IHP)
if: "${{ matrix.pdk == 'ihp-sg13g2' }}"
if: "${{ matrix.pdk == 'ihp-sg13cmos5l' }}"
run: echo "TT_TOOL_ARGS=--ihp" >> $GITHUB_ENV
- name: Configure tt_tool.py args (gf180mcuD)
config.py
+1 -1
View File
@@ -17,7 +17,7 @@ class DatasheetConfig(TypedDict):
"caravel",
"openframe",
"openframe_sky130",
"customframe_ihp_sg13g2",
"customframe_ihp_sg13cmos5l",
"customframe_gf180mcud",
]
theme_override_colour: str
doc_utils.py
+3 -3
View File
@@ -434,8 +434,8 @@ class DocsHelper:
case "sky130A":
content["pinout"] = "openframe_sky130"
case "ihp-sg13g2":
content["pinout"] = "customframe_ihp_sg13g2"
case "ihp-sg13cmos5l":
content["pinout"] = "customframe_ihp_sg13cmos5l"
case "gf180mcuD":
content["pinout"] = "customframe_gf180mcud"
case _:
@@ -451,7 +451,7 @@ class DocsHelper:
content["pinout"] = "openframe_sky130"
elif shuttle_config["id"].startswith("ttihp"):
content["pinout"] = "customframe_ihp_sg13g2"
content["pinout"] = "customframe_ihp_sg13cmos5l"
elif shuttle_config["id"].startswith("ttgf"):
content["pinout"] = "customframe_gf180mcud"
docs/typst/chapters/pinout-tables.typ
+1 -1
View File
@@ -227,7 +227,7 @@
]
}
#let customframe_ihp_sg13g2 = {
#let customframe_ihp_sg13cmos5l = {
align(center,
table(
columns: 4,
docs/typst/src/datasheet.typ
+1 -1
View File
@@ -483,7 +483,7 @@
caravel: (diagram: "chip_pinout_qfn64", table: pins.caravel),
openframe: (diagram: "chip_pinout_qfn64", table: pins.openframe),
openframe_sky130: (diagram: "chip_pinout_qfn64_sky130_openframe", table: pins.openframe_sky130),
customframe_ihp_sg13g2: (diagram: "chip_pinout_qfn64_ihp_sg13g2", table: pins.customframe_ihp_sg13g2),
customframe_ihp_sg13cmos5l: (diagram: "chip_pinout_qfn64_ihp_sg13cmos5l", table: pins.customframe_ihp_sg13cmos5l),
customframe_gf180mcud: (diagram: "chip_pinout_qfn64_gf180mcud", table: pins.customframe_gf180mcud)
)
logo.py
+1 -1
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@@ -119,7 +119,7 @@ if __name__ == "__main__":
"--pdk",
type=str,
default="sky130A",
choices=["sky130A", "ihp-sg13g2", "gf180mcuD"],
choices=["sky130A", "ihp-sg13cmos5l", "gf180mcuD"],
)
parser.add_argument("--top", action="store_true")
parser.add_argument("--bottom", action="store_true")
precheck/klayout_tools.py
+1 -1
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@@ -54,7 +54,7 @@ def parse_lyp_layers(lyp_file: str, only_valid: bool = True):
if " " in source:
assert source.count(" ") == 1
# sky130A and sg13g2 has the name in the "name" field
# sky130A and sg13cmos5l has the name in the "name" field
# gf180mcuD has the name as part of the "source" field
# if a future PDK has it in both places, we'll trigger the
# assertion below to decide which one has priority
precheck/precheck.py
+7 -7
View File
@@ -112,11 +112,11 @@ def klayout_zero_area(gds: str):
return klayout_drc(gds, "zero_area", "zeroarea.rb.drc")
def klayout_sg13g2(gds: str):
def klayout_sg13cmos5l(gds: str):
return klayout_drc(
gds,
"sg13g2",
f"{PDK_ROOT}/{PDK_NAME}/libs.tech/klayout/tech/drc/ihp-sg13g2.drc",
"sg13cmos5l",
f"{PDK_ROOT}/{PDK_NAME}/libs.tech/klayout/tech/drc/ihp-sg13cmos5l.drc",
)
@@ -367,7 +367,7 @@ def main():
template_def = f"{def_root}/analog/tt_analog_{tiles}_3v3.def"
else:
template_def = f"{def_root}/analog/tt_analog_{tiles}.def"
elif tech == "ihp-sg13g2" or tech == "gf180mcuD":
elif tech == "ihp-sg13cmos5l" or tech == "gf180mcuD":
template_def = f"{def_root}/tt_block_{tiles}_pgvdd.def"
else:
template_def = f"{def_root}/tt_block_{tiles}_pg.def"
@@ -413,8 +413,8 @@ def main():
},
{
"name": "KLayout SG13G2 DRC",
"check": lambda: klayout_sg13g2(gds_file),
"techs": ["ihp-sg13g2"],
"check": lambda: klayout_sg13cmos5l(gds_file),
"techs": ["ihp-sg13cmos5l"],
},
{"name": "KLayout zero area", "check": lambda: klayout_zero_area(gds_file)},
{
@@ -445,7 +445,7 @@ def main():
"check": lambda: analog_pin_check(
gds_file, tech, is_analog, uses_3v3, analog_pins, pinout
),
"techs": ["sky130A", "ihp-sg13g2"],
"techs": ["sky130A", "ihp-sg13cmos5l"],
},
]
precheck/reports/.gitignore
+1 -1
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@@ -4,7 +4,7 @@ drc_offgrid.xml
drc_pin_label_purposes_overlapping_drawing.xml
drc_zero_area.xml
drc_nwell_urpm.xml
drc_sg13g2.xml
drc_sg13cmos5l.xml
magic_drc.mag
magic_drc.txt
results.md
precheck/tech-files/README.txt
+1 -1
View File
@@ -3,7 +3,7 @@ pin_label_purposes_overlapping_drawing.rb.drc from https://github.com/chipfoundr
zeroarea.rb.drc from https://github.com/chipfoundry/mpw_precheck revision 4fd5283b124e931c9e71219f47270075176f84e2
nwell_urpm.drc from https://open-source-silicon.slack.com/archives/C05FW1VMY5A/p1729112262642699?thread_ts=1728921677.220509&cid=C05FW1VMY5A
sg13g2_mr.lydrc:
sg13cmos5l_mr.lydrc:
from https://github.com/IHP-GmbH/TO_Apr2025 revision 772a369f3ceabc2c6e1eba57d91ae755682c8323
with the following minimum density rules disabled:
- M1.j, M2.j, M3.j, M4.j, M5.j
precheck/tech_data.py
+21 -26
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@@ -1,4 +1,4 @@
tech_names = ["sky130A", "ihp-sg13g2", "gf180mcuD"]
tech_names = ["sky130A", "ihp-sg13cmos5l", "gf180mcuD"]
# fmt: off
valid_layers_sky130A = [
@@ -56,7 +56,7 @@ valid_layers_sky130A = [
(235, 0), (235, 250), (235, 252), (236, 0),
]
valid_layers_ihp_sg13g2 = [
valid_layers_ihp_sg13cmos5l = [
"Substrate.drawing", "Substrate.text", "Activ.drawing", "Activ.label", "Activ.nofill", "Activ.pin", "GatPoly.drawing",
"GatPoly.label", "GatPoly.nofill", "GatPoly.pin", "PolyRes.drawing", "PolyRes.label", "PolyRes.pin", "NWell.drawing",
"NWell.label", "NWell.pin", "nBuLay.drawing", "nBuLay.label", "nBuLay.pin", "nBuLay.block", "PWell.block",
@@ -65,17 +65,14 @@ valid_layers_ihp_sg13g2 = [
"Metal2.drawing", "Metal2.label", "Metal2.nofill", "Metal2.pin", "Metal2.slit", "Metal2.text", "Metal2.res",
"Via2.drawing", "Via2.net", "Via2.boundary", "Metal3.drawing", "Metal3.label", "Metal3.nofill", "Metal3.pin",
"Metal3.slit", "Metal3.text", "Metal3.res", "MIM.drawing", "Vmim.drawing", "Via3.drawing", "Metal4.drawing",
"Metal4.label", "Metal4.nofill", "Metal4.pin", "Metal4.slit", "Metal4.text", "Metal4.res", "Via4.drawing",
"Metal5.drawing", "Metal5.label", "Metal5.nofill", "Metal5.pin", "Metal5.slit", "Metal5.text", "Metal5.res",
"TopVia1.drawing", "TopMetal1.drawing", "TopMetal1.label", "TopMetal1.nofill", "TopMetal1.pin", "TopMetal1.slit",
"TopMetal1.text", "TopMetal1.res", "TopMetal2.nofill", "IND.drawing", "IND.pin", "IND.boundary", "IND.text",
"TEXT.drawing", "Recog.drawing", "Recog.pin", "Recog.esd", "Recog.diode", "Recog.tsv", "Recog.pdiode", "Recog.mom",
"DigiBnd.drawing", "DigiBnd.drawing0", "RES.drawing", "RES.label", "SRAM.drawing", "SRAM.label", "SRAM.boundary",
"DigiSub.drawing", "HeatRes.drawing", "NoRCX.drawing", "NoRCX.m2m3", "NoRCX.m2m4", "NoRCX.m2m5", "NoRCX.m2tm1",
"NoRCX.m2tm2", "NoRCX.m3m4", "NoRCX.m3m5", "NoRCX.m3tm1", "NoRCX.m3tm2", "NoRCX.m4m5", "NoRCX.m4tm1", "NoRCX.m4tm2",
"NoRCX.m5tm1", "NoRCX.m5tm2", "NoRCX.tm1tm2", "NoRCX.m1sub", "NoRCX.m2sub", "NoRCX.m3sub", "NoRCX.m4sub", "NoRCX.m5sub",
"NoRCX.tm1sub", "Varicap.drawing", "EXTBlock.drawing", "prBoundary.drawing", "prBoundary.label", "prBoundary.boundary",
"isoNWell.drawing",
"Metal4.label", "Metal4.nofill", "Metal4.pin", "Metal4.slit", "Metal4.text", "Metal4.res", "TopMetal1.nofill",
"IND.drawing", "IND.pin", "IND.boundary", "IND.text", "TEXT.drawing", "Recog.drawing", "Recog.pin", "Recog.esd",
"Recog.diode", "Recog.tsv", "Recog.pdiode", "Recog.mom", "DigiBnd.drawing", "DigiBnd.drawing0", "RES.drawing",
"RES.label", "SRAM.drawing", "SRAM.label", "SRAM.boundary", "DigiSub.drawing", "HeatRes.drawing", "NoRCX.drawing",
"NoRCX.m2m3", "NoRCX.m2m4", "NoRCX.m2m5", "NoRCX.m2tm1", "NoRCX.m2tm2", "NoRCX.m3m4", "NoRCX.m3m5", "NoRCX.m3tm1",
"NoRCX.m3tm2", "NoRCX.m4m5", "NoRCX.m4tm1", "NoRCX.m4tm2", "NoRCX.m5tm1", "NoRCX.m5tm2", "NoRCX.tm1tm2", "NoRCX.m1sub",
"NoRCX.m2sub", "NoRCX.m3sub", "NoRCX.m4sub", "NoRCX.m5sub", "NoRCX.tm1sub", "Varicap.drawing", "EXTBlock.drawing",
"prBoundary.drawing", "prBoundary.label", "prBoundary.boundary", "isoNWell.drawing",
]
valid_layers_gf180mcuD = [
@@ -108,7 +105,7 @@ def analog_pin_rects(tech: str, uses_3v3: bool):
x2, y2 = x1 + 0.9, y1 + 1.0
rect = ((x1, y1), (x2, y2))
yield (rect, pin_layer, via_layers)
elif tech == "ihp-sg13g2":
elif tech == "ihp-sg13cmos5l":
pin_layer = (126, 0) # TopMetal1
via_layers = [(125, 0)] # TopVia1
for pin_number in range(8):
@@ -127,12 +124,12 @@ def analog_pin_rects(tech: str, uses_3v3: bool):
valid_layers = {
"sky130A": valid_layers_sky130A,
"ihp-sg13g2": valid_layers_ihp_sg13g2,
"ihp-sg13cmos5l": valid_layers_ihp_sg13cmos5l,
"gf180mcuD": valid_layers_gf180mcuD,
}
lyp_filename = {
"sky130A": "sky130A.lyp",
"ihp-sg13g2": "sg13g2.lyp",
"ihp-sg13cmos5l": "sg13cmos5l.lyp",
"gf180mcuD": "gf180mcu.lyp",
}
@@ -144,13 +141,11 @@ valid_lef_port_layers = {
"met3.pin": (70, 16),
"met4.pin": (71, 16),
},
"ihp-sg13g2": {
"ihp-sg13cmos5l": {
"Metal1.pin": (8, 2),
"Metal2.pin": (10, 2),
"Metal3.pin": (30, 2),
"Metal4.pin": (50, 2),
"Metal5.pin": (67, 2),
"TopMetal1.pin": (126, 2),
},
}
forbidden_layers = {
@@ -159,10 +154,10 @@ forbidden_layers = {
"met5.pin",
"met5.label",
],
"ihp-sg13g2": [
"TopMetal2.drawing",
"TopMetal2.pin",
"TopMetal2.label",
"ihp-sg13cmos5l": [
"TopMetal1.drawing",
"TopMetal1.pin",
"TopMetal1.label",
],
"gf180mcuD": [
"Metal5",
@@ -171,16 +166,16 @@ forbidden_layers = {
}
power_pins_layer = {
"sky130A": "met4",
"ihp-sg13g2": "TopMetal1",
"ihp-sg13cmos5l": "Metal4",
"gf180mcuD": "Metal4",
}
power_pins_min_width = {
"sky130A": 1200, # 1.2 um
"ihp-sg13g2": 2100, # 2.1 um
"ihp-sg13cmos5l": 2100, # 2.1 um
"gf180mcuD": 1200, # 1.2 um
}
boundary_layer = {
"sky130A": "prBoundary.boundary",
"ihp-sg13g2": "prBoundary.boundary",
"ihp-sg13cmos5l": "prBoundary.boundary",
"gf180mcuD": "PR_bndry",
}
rom/config.json
+3 -3
View File
@@ -36,9 +36,9 @@
"RUN_KLAYOUT_DRC": false
},
"pdk::ihp-sg13g2": {
"pdk::ihp-sg13cmos5l": {
"DIE_AREA": [0, 0, 202.08, 154.98],
"FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../tech/ihp-sg13g2/def/tt_block_1x1_pgvdd.def",
"RT_MAX_LAYER": "Metal5"
"FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../tech/ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def",
"RT_MAX_LAYER": "Metal4"
}
}
tech.py
+20 -20
View File
@@ -2,7 +2,7 @@ import json
import os
from typing import Dict, List, Literal, Pattern, Protocol, Tuple, TypedDict, Union
TechName = Literal["sky130A", "ihp-sg13g2", "gf180mcuD", "fpgaUp5k"]
TechName = Literal["sky130A", "ihp-sg13cmos5l", "gf180mcuD", "fpgaUp5k"]
class CellDefinition(TypedDict):
@@ -128,16 +128,16 @@ class Sky130Tech(Tech):
class IHPTech(Tech):
is_fpga = False
def_suffix = "pgvdd"
librelane_pdk_args = "--pdk ihp-sg13g2"
librelane_pdk_args = "--pdk ihp-sg13cmos5l --manual-pdk"
tt_corner = "nom_typ_1p20V_25C"
cell_regexp = r"^\s*sg13g2_(?P<cell_name>\S+)_(?P<cell_drive>\d+)"
cell_regexp = r"^\s*sg13cmos5l_(?P<cell_name>\S+)_(?P<cell_drive>\d+)"
netlist_type = "nl"
project_top_metal_layer = "TopMetal1"
project_top_metal_layer = "Metal4"
librelane_config = {}
label_layers = [
(8, 1), # Metal1.label
(8, 25), # Metal1.text
(67, 25), # Metal5.text
(50, 25), # Metal4.text
(126, 25), # TopMetal1.text
]
buried_layers = [
@@ -147,32 +147,32 @@ class IHPTech(Tech):
(51, 0), # HeatTrans.drawing
(189, 4), # prBoundary.boundary
]
scramble_cells = "sg13g2_"
mux_config_yaml_name = "ihp-sg13g2.yaml"
scramble_cells = "sg13cmos5l_"
mux_config_yaml_name = "ihp-sg13cmos5l.yaml"
mux_macros = [
"pg/ihp-sg13g2/tt_pg_1v5_hp_1",
"pg/ihp-sg13g2/tt_pg_1v5_hp_2",
"pg/ihp-sg13g2/tt_pg_1v5_hp_4",
"pg/ihp-sg13g2/tt_pg_1v5_ll_1",
"pg/ihp-sg13g2/tt_pg_1v5_ll_2",
"pg/ihp-sg13g2/tt_pg_1v5_ll_4",
"pg/ihp-sg13cmos5l/tt_pg_1v5_hp_1",
"pg/ihp-sg13cmos5l/tt_pg_1v5_hp_2",
"pg/ihp-sg13cmos5l/tt_pg_1v5_hp_4",
"pg/ihp-sg13cmos5l/tt_pg_1v5_ll_1",
"pg/ihp-sg13cmos5l/tt_pg_1v5_ll_2",
"pg/ihp-sg13cmos5l/tt_pg_1v5_ll_4",
]
extra_logo_macros = [
"tech/ihp-sg13g2/tt_logo_corner",
"tech/ihp-sg13cmos5l/tt_logo_corner",
]
prboundary_layer = (189, 4) # prBoundary.boundary
logo_layer = (67, 0) # Metal5.drawing
logo_layer_name = "Metal5"
logo_layer = (50, 0) # Metal4.drawing
logo_layer_name = "Metal4"
logo_pixel_size = 0.25 # um
def read_pdk_version(self, pdk_root: str) -> PDKVersionInfo:
pdk_sources_file = os.path.join(pdk_root, "ihp-sg13g2", "SOURCES")
pdk_sources_file = os.path.join(pdk_root, "ihp-sg13cmos5l", "SOURCES")
return parse_openpdks_pdk_version(pdk_sources_file, "IHP-Open-PDK")
def load_cell_definitions(self) -> Dict[str, CellDefinition]:
URL_FORMAT = "https://raw.githubusercontent.com/IHP-GmbH/IHP-Open-PDK/refs/heads/main/ihp-sg13g2/libs.ref/sg13g2_stdcell/doc/sg13g2_stdcell_typ_1p20V_25C.pdf#{ref}"
URL_FORMAT = "https://raw.githubusercontent.com/IHP-GmbH/IHP-Open-PDK/refs/heads/main/ihp-sg13cmos5l/libs.ref/sg13cmos5l_stdcell/doc/sg13cmos5l_stdcell_typ_1p20V_25C.pdf#{ref}"
script_dir = os.path.dirname(os.path.realpath(__file__))
with open(os.path.join(script_dir, "tech/ihp-sg13g2/cells.json")) as fh:
with open(os.path.join(script_dir, "tech/ihp-sg13cmos5l/cells.json")) as fh:
cells = json.load(fh)
for cell in cells.values():
cell["url"] = URL_FORMAT.format(ref=cell["doc_ref"])
@@ -277,7 +277,7 @@ class FpgaTech(Tech):
tech_map: dict[TechName, Tech] = {
"ihp-sg13g2": IHPTech(),
"ihp-sg13cmos5l": IHPTech(),
"gf180mcuD": GF180MCUDTech(),
"sky130A": Sky130Tech(),
"fpgaUp5k": FpgaTech(),
tech/ihp-sg13g2/categories.json → tech/ihp-sg13cmos5l/categories.json
View File
tech/ihp-sg13g2/cells.json → tech/ihp-sg13cmos5l/cells.json
View File
tech/ihp-sg13g2/def/analog/magic_init_project.tcl → tech/ihp-sg13cmos5l/def/analog/magic_init_project.tcl
+1 -1
View File
@@ -4,7 +4,7 @@
# Description: This script initializes a new Magic project for an analog design on Tiny Tapeout.
# Important: before running this script, download the the .def file from
# https://raw.githubusercontent.com/TinyTapeout/tt-support-tools/main/tech/ihp-sg13g2/def/analog/tt_analog_1x2.def
# https://raw.githubusercontent.com/TinyTapeout/tt-support-tools/main/tech/ihp-sg13cmos5l/def/analog/tt_analog_1x2.def
# Change the settings below to match your design:
# ------------------------------------------------
tech/ihp-sg13g2/def/analog/tt_analog_1x2.def → tech/ihp-sg13cmos5l/def/analog/tt_analog_1x2.def
-4
View File
@@ -93,12 +93,8 @@ TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 88 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 50 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 51 ;
tech/ihp-sg13g2/def/analog/tt_analog_2x2.def → tech/ihp-sg13cmos5l/def/analog/tt_analog_2x2.def
-4
View File
@@ -93,12 +93,8 @@ TRACKS X 480 DO 873 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 183 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 105 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 51 ;
tech/ihp-sg13g2/def/tt_block_1x1_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def
-4
View File
@@ -51,12 +51,8 @@ TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 88 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 50 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_1x2_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_1x2_pgvdd.def
-4
View File
@@ -93,12 +93,8 @@ TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 88 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 50 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_2x2_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_2x2_pgvdd.def
-4
View File
@@ -93,12 +93,8 @@ TRACKS X 480 DO 873 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 183 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 105 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_3x2_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_3x2_pgvdd.def
-4
View File
@@ -93,12 +93,8 @@ TRACKS X 480 DO 1326 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 279 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 159 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_3x4_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_3x4_pgvdd.def
-4
View File
@@ -198,12 +198,8 @@ TRACKS X 480 DO 1326 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1326 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 279 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 159 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 177 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_4x2_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_4x2_pgvdd.def
-4
View File
@@ -93,12 +93,8 @@ TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 374 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 213 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_4x4_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_4x4_pgvdd.def
-4
View File
@@ -198,12 +198,8 @@ TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 374 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 213 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 177 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_5x4_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_5x4_pgvdd.def
-4
View File
@@ -198,12 +198,8 @@ TRACKS X 480 DO 2232 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 2232 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2232 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 470 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 268 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 177 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_6x2_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_6x2_pgvdd.def
-4
View File
@@ -93,12 +93,8 @@ TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 565 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_6x4_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_6x4_pgvdd.def
-4
View File
@@ -198,12 +198,8 @@ TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 565 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 177 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/def/tt_block_8x2_pgvdd.def → tech/ihp-sg13cmos5l/def/tt_block_8x2_pgvdd.def
-4
View File
@@ -93,12 +93,8 @@ TRACKS X 480 DO 3591 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 3591 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 3591 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 756 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 431 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
tech/ihp-sg13g2/tile_sizes.yaml → tech/ihp-sg13cmos5l/tile_sizes.yaml
View File
tech/ihp-sg13cmos5l/tt_logo_corner.gds
BIN
View File
Binary file not shown.
tech/ihp-sg13g2/tt_logo_corner.lef → tech/ihp-sg13cmos5l/tt_logo_corner.lef
+1 -1
View File
@@ -8,7 +8,7 @@ MACRO tt_logo_corner
ORIGIN 0.000 0.000 ;
SIZE 100.000 BY 100.000 ;
OBS
LAYER TopMetal2 ;
LAYER TopMetal1 ;
RECT 45.000 99.500 55.000 100.000 ;
RECT 41.500 99.000 58.500 99.500 ;
RECT 39.000 98.500 61.000 99.000 ;
tech/ihp-sg13g2/tt_logo_corner.v → tech/ihp-sg13cmos5l/tt_logo_corner.v
View File
tech/ihp-sg13g2/tt_logo_corner.gds
BIN
View File
Binary file not shown.
tt_tool.py
+3 -1
View File
@@ -147,7 +147,9 @@ if __name__ == "__main__":
setup_logging(args.loglevel)
pdk: TechName = "ihp-sg13g2" if args.ihp else "gf180mcuD" if args.gf else "sky130A"
pdk: TechName = (
"ihp-sg13cmos5l" if args.ihp else "gf180mcuD" if args.gf else "sky130A"
)
if args.check_docs:
check_project_docs(args.project_dir, pdk)