test framework

This commit is contained in:
psychogenic
2023-04-11 02:25:33 -04:00
parent 6bc50e5340
commit ddee08c805
7 changed files with 840 additions and 8 deletions
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# Makefile
# See https://docs.cocotb.org/en/stable/quickstart.html for more info
# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog
# normal simulation
ifneq ($(GATES),yes)
# this is the only part you should need to modify:
VERILOG_SOURCES += $(PWD)/cells.v $(PWD)/user_module_WOKWI_ID.v $(PWD)/test_wokwi.v
else
# gate level simulation requires some extra setup, you shouldn't need to touch this
COMPILE_ARGS += -DGL_TEST
COMPILE_ARGS += -DFUNCTIONAL
COMPILE_ARGS += -DUSE_POWER_PINS
COMPILE_ARGS += -DSIM
COMPILE_ARGS += -DUNIT_DELAY=#1
VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
# this gets copied in by the GDS action workflow
VERILOG_SOURCES += $(PWD)/test_wokwi.v $(PWD)/gate_level_netlist.v
endif
# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = test_wokwi
# MODULE is the basename of the Python test file
MODULE = test
# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim
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'''
Wokwi TinyTapeout truth-table based auto test sequence.
SPDX-FileCopyrightText: © 2023 Pat Deegan, https://psychogenic.com
SPDX-License-Identifier: Apache2.0
'''
import os
import cocotb
import testutils.truthtable as truthtable
@cocotb.test()
async def truthTableCompare(parentDUT):
'''
truthTableCompare -- loads markdown truth table and, if load succeeded, actually performs the tests.
'''
usermodule = parentDUT.dut
i_bus = parentDUT.io_in
o_bus = parentDUT.io_out
tt = truthtable.loadMarkdownTruthTable('truthtable.md', usermodule._log)
if tt is None:
usermodule._log.info('No truth table loaded, no table compare test to run')
return
usermodule._log.debug(str(tt))
await tt.testAll(i_bus, o_bus, usermodule._log)
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// SPDX-License-Identifier: Apache2.0
`timescale 1ns / 1ps
`default_nettype none
module test_wokwi ();
wire [7:0] io_out;
wire [7:0] io_in;
user_module_WOKWI_ID dut (
`ifdef GL_TEST
.vccd1( 1'b1),
.vssd1( 1'b0),
`endif
.io_in (io_in),
.io_out(io_out)
);
initial begin
$dumpfile("wokwi_tb_WOKWI_ID.vcd");
$dumpvars(0, test_wokwi);
end
endmodule