From e96fa6fc6f67e90088b942be3d6bfb57e5456b3c Mon Sep 17 00:00:00 2001 From: htfab Date: Mon, 1 Sep 2025 23:26:45 +0200 Subject: [PATCH] fix(precheck): use non-greedy regex for stripping verilog comments as suggested by @smunaut --- precheck/precheck.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/precheck/precheck.py b/precheck/precheck.py index 57a8b29..f7a1351 100644 --- a/precheck/precheck.py +++ b/precheck/precheck.py @@ -161,7 +161,7 @@ def power_pin_check(verilog: str, lef: str, uses_3v3: bool): # naive but good enough way to ignore comments verilog_s = re.sub("//.*", "", verilog_s) - verilog_s = re.sub("/\\*.*\\*/", "", verilog_s, flags=(re.DOTALL | re.MULTILINE)) + verilog_s = re.sub("/\\*.*?\\*/", "", verilog_s, flags=(re.DOTALL | re.MULTILINE)) for ft, s in (("Verilog", verilog_s), ("LEF", lef_s)): for pwr, ex in (("VGND", True), ("VDPWR", True), ("VAPWR", uses_3v3)):