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refactor: rename uses_3v3 to uses_vapwr

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The flag enables a second power supply (VAPWR), not necessarily 3.3V (gf180's core is already 3v3), so "uses_3v3" no longer accurately describes its purpose.
Rename it across project_info, precheck, project and shuttle, and update the validation message accordingly.

The legacy "uses_3v3" key is still accepted when reading info.yaml, so existing project configs keep working.
This commit is contained in:
Uri Shaked
2026-05-31 16:18:24 +03:00
parent d5b156e241
commit ed26854793
8 changed files with 64 additions and 43 deletions
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precheck/test_precheck.py
+4 -4
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@@ -697,13 +697,13 @@ def test_shapes_outside_area(gds_shapes_outside_area: str):
def test_wrong_power_pins_1(verilog_lef_wrong_power_pins: tuple[str, str]):
verilog_file, lef_file = verilog_lef_wrong_power_pins
with pytest.raises(precheck.PrecheckFailure, match="Verilog contains VAPWR"):
precheck.power_pin_check(verilog_file, lef_file, uses_3v3=False)
precheck.power_pin_check(verilog_file, lef_file, uses_vapwr=False)
def test_wrong_power_pins_2(verilog_lef_wrong_power_pins: tuple[str, str]):
verilog_file, lef_file = verilog_lef_wrong_power_pins
with pytest.raises(precheck.PrecheckFailure, match="LEF doesn't contain VAPWR"):
precheck.power_pin_check(verilog_file, lef_file, uses_3v3=True)
precheck.power_pin_check(verilog_file, lef_file, uses_vapwr=True)
def test_missing_use_power(verilog_lef_missing_use_power: tuple[str, str]):
@@ -712,7 +712,7 @@ def test_missing_use_power(verilog_lef_missing_use_power: tuple[str, str]):
precheck.PrecheckFailure,
match="VDPWR does not have a corresponding 'USE POWER ;'",
):
precheck.power_pin_check(verilog_file, lef_file, uses_3v3=False)
precheck.power_pin_check(verilog_file, lef_file, uses_vapwr=False)
def test_missing_use_ground(verilog_lef_missing_use_ground: tuple[str, str]):
@@ -721,7 +721,7 @@ def test_missing_use_ground(verilog_lef_missing_use_ground: tuple[str, str]):
precheck.PrecheckFailure,
match="VGND does not have a corresponding 'USE GROUND ;'",
):
precheck.power_pin_check(verilog_file, lef_file, uses_3v3=False)
precheck.power_pin_check(verilog_file, lef_file, uses_vapwr=False)
def test_invalid_layer(gds_invalid_layer: str):