From f8cc66a644071ca47cfc65213500107ab05a4660 Mon Sep 17 00:00:00 2001 From: htfab Date: Tue, 24 Sep 2024 02:25:23 +0200 Subject: [PATCH] feat: add experimental IHP support --- cells.py | 19 ++- config_utils.py | 47 +++++- ihp/categories.json | 67 ++++++++ ihp/cells.json | 232 +++++++++++++++++++++++++++ ihp/constraint.sdc | 13 ++ ihp/def/tt_block_1x1.def | 285 ++++++++++++++++++++++++++++++++++ ihp/def/tt_block_1x2.def | 327 +++++++++++++++++++++++++++++++++++++++ ihp/def/tt_block_2x1.def | 285 ++++++++++++++++++++++++++++++++++ ihp/def/tt_block_2x2.def | 327 +++++++++++++++++++++++++++++++++++++++ ihp/def/tt_block_3x1.def | 285 ++++++++++++++++++++++++++++++++++ ihp/def/tt_block_3x2.def | 327 +++++++++++++++++++++++++++++++++++++++ ihp/def/tt_block_4x1.def | 285 ++++++++++++++++++++++++++++++++++ ihp/def/tt_block_4x2.def | 327 +++++++++++++++++++++++++++++++++++++++ ihp/def/tt_block_6x1.def | 285 ++++++++++++++++++++++++++++++++++ ihp/def/tt_block_6x2.def | 327 +++++++++++++++++++++++++++++++++++++++ ihp/def/tt_block_8x1.def | 285 ++++++++++++++++++++++++++++++++++ ihp/def/tt_block_8x2.def | 327 +++++++++++++++++++++++++++++++++++++++ ihp/pdn.tcl | 18 +++ ihp/tile_sizes.yaml | 12 ++ project.py | 281 ++++++++++++++++++++++++++------- tt_tool.py | 7 + 21 files changed, 4308 insertions(+), 60 deletions(-) create mode 100644 ihp/categories.json create mode 100644 ihp/cells.json create mode 100644 ihp/constraint.sdc create mode 100644 ihp/def/tt_block_1x1.def create mode 100644 ihp/def/tt_block_1x2.def create mode 100644 ihp/def/tt_block_2x1.def create mode 100644 ihp/def/tt_block_2x2.def create mode 100644 ihp/def/tt_block_3x1.def create mode 100644 ihp/def/tt_block_3x2.def create mode 100644 ihp/def/tt_block_4x1.def create mode 100644 ihp/def/tt_block_4x2.def create mode 100644 ihp/def/tt_block_6x1.def create mode 100644 ihp/def/tt_block_6x2.def create mode 100644 ihp/def/tt_block_8x1.def create mode 100644 ihp/def/tt_block_8x2.def create mode 100644 ihp/pdn.tcl create mode 100644 ihp/tile_sizes.yaml diff --git a/cells.py b/cells.py index 8bfb2bf..724c1e6 100644 --- a/cells.py +++ b/cells.py @@ -10,7 +10,7 @@ class Port(TypedDict): description: str -class Cell(TypedDict): +class Sky130Cell(TypedDict): description: str file_prefix: str library: str @@ -22,10 +22,23 @@ class Cell(TypedDict): equation: Optional[str] -Cells = Dict[str, Cell] +class IHPCell(TypedDict): + description: str + doc_name: str + doc_ref: int -def load_cells() -> Cells: +Sky130Cells = Dict[str, Sky130Cell] +IHPCells = Dict[str, IHPCell] + + +def load_sky130_cells() -> Sky130Cells: script_dir = os.path.dirname(os.path.realpath(__file__)) with open(os.path.join(script_dir, "cells.json")) as fh: return json.load(fh) + + +def load_ihp_cells() -> IHPCells: + script_dir = os.path.dirname(os.path.realpath(__file__)) + with open(os.path.join(script_dir, "ihp/cells.json")) as fh: + return json.load(fh) diff --git a/config_utils.py b/config_utils.py index 0ba0025..1f4083b 100644 --- a/config_utils.py +++ b/config_utils.py @@ -2,6 +2,7 @@ import json import logging import os import re +import subprocess import tkinter from collections.abc import Iterable @@ -42,13 +43,43 @@ def read_tcl_config(file: str, design_dir: str | None = None): def read_json_config(file: str): - return json.load(open(file)) + config = json.load(open(file)) + config.pop("//", None) + return config def read_yaml_config(file: str): return yaml.safe_load(open(file)) +def read_mk_config(file: str, design_dir: str | None = None): + logging.warning( + "Reading Makefile configuration files is an experimental feature and could be removed" + ) + env_pre = {} if design_dir is None else {"DESIGN_HOME": design_dir} + mk_cg = "all:\n\t@env" + mk_tg = f"-include {file}\n{mk_cg}" + env_cg = subprocess.run( + "make -f -", + shell=True, + env=env_pre, + input=mk_cg, + capture_output=True, + text=True, + ).stdout.strip() + env_tg = subprocess.run( + "make -f -", + shell=True, + env=env_pre, + input=mk_tg, + capture_output=True, + text=True, + ).stdout.strip() + env_diff = set(env_tg.split("\n")) - set(env_cg.split("\n")) + config = dict(i.split("=", 1) for i in env_diff) + return config + + def read_config(basename: str, formats: Iterable[str], design_dir: str | None = None): for fmt in formats: file = f"{basename}.{fmt}" @@ -59,6 +90,8 @@ def read_config(basename: str, formats: Iterable[str], design_dir: str | None = return read_json_config(file) elif fmt == "yaml": return read_yaml_config(file) + elif fmt == "mk": + return read_mk_config(file) else: raise ConfigFileError(f"Unexpected configuration file format: {fmt}") raise ConfigFileError( @@ -89,6 +122,16 @@ def write_yaml_config(config: dict, file: str): yaml.safe_dump(config, f, default_flow_style=False, sort_keys=False) +def write_mk_config(config: dict, file: str): + with open(file, "w") as f: + for key, value in config.items(): + if type(value) in (list, tuple): + value = " ".join(value) + if type(value) == str: + value = value.replace("dir::", "$(DESIGN_HOME)/") + print(f"export {key} = {value}", file=f) + + def write_config(config: dict, basename: str, formats: Iterable[str]): for fmt in formats: file = f"{basename}.{fmt}" @@ -98,5 +141,7 @@ def write_config(config: dict, basename: str, formats: Iterable[str]): write_json_config(config, file) elif fmt == "yaml": write_yaml_config(config, file) + elif fmt == "mk": + write_mk_config(config, file) else: raise ConfigFileError("Unexpected configuration file format: {fmt}") diff --git a/ihp/categories.json b/ihp/categories.json new file mode 100644 index 0000000..9dd5ff1 --- /dev/null +++ b/ihp/categories.json @@ -0,0 +1,67 @@ +{ + "categories" : [ + "AND", + "OR", + "NAND", + "NOR", + "Clock", + "Flip Flops", + "Multiplexer", + "Latch", + "Inverter", + "Buffer", + "Fill", + "Tap", + "Diode", + "Combo Logic", + "Misc" + ], + "map" : { + "a21o" : 13, + "a21oi" : 13, + "a22oi" : 13, + "a221oi" : 13, + "and2" : 0, + "and3" : 0, + "and4" : 0, + "antennanp" : 12, + "buf" : 9, + "decap" : 10, + "dfrbp" : 5, + "dlhq" : 7, + "dlhr" : 7, + "dlhrq" : 7, + "dllr" : 7, + "dllrq" : 7, + "dlygate4sd1" : 14, + "dlygate4sd2" : 14, + "dlygate4sd3" : 14, + "ebufn" : 14, + "einvn" : 14, + "fill" : 10, + "inv" : 8, + "lgcp" : 4, + "mux2" : 6, + "mux4" : 6, + "nand2" : 2, + "nand2b" : 2, + "nand3" : 2, + "nand3b" : 2, + "nand4" : 2, + "nor2" : 3, + "nor2b" : 3, + "nor3" : 3, + "nor4" : 3, + "o21ai" : 13, + "or2" : 1, + "or3" : 1, + "or4" : 1, + "sdfbbp" : 5, + "sighold" : 14, + "slgcp" : 4, + "tiehi" : 14, + "tielo" : 14, + "xnor2" : 3, + "xor2" : 1 + } +} diff --git a/ihp/cells.json b/ihp/cells.json new file mode 100644 index 0000000..ca9d5f1 --- /dev/null +++ b/ihp/cells.json @@ -0,0 +1,232 @@ +{ + "a21o" : { + "description" : "2-input AND into first input of 2-input OR.", + "doc_name": "AO21x", + "doc_ref" : 7 + }, + "a21oi" : { + "description" : "2-input AND into first input of 2-input NOR.", + "doc_name": "A21OIx", + "doc_ref" : 1 + }, + "a221oi" : { + "description" : "2-input AND into first two inputs of 3-input NOR.", + "doc_name": "A221OI", + "doc_ref" : 2 + }, + "a22oi" : { + "description" : "2-input AND into both inputs of 2-input NOR.", + "doc_name": "A22OI", + "doc_ref" : 3 + }, + "and2" : { + "description" : "2-input AND.", + "doc_name": "AND2x", + "doc_ref" : 4 + }, + "and3" : { + "description" : "3-input AND.", + "doc_name": "AND3x", + "doc_ref" : 5 + }, + "and4" : { + "description" : "4-input AND.", + "doc_name": "AND4x", + "doc_ref" : 6 + }, + "antennanp" : { + "description" : "Antenna tie-down diode.", + "doc_name": "NP_ANT", + "doc_ref" : 38 + }, + "buf" : { + "description" : "Buffer.", + "doc_name": "BUx", + "doc_ref" : 9 + }, + "decap" : { + "description" : "Decoupling capacitance filler.", + "doc_name": "DECAPx", + "doc_ref" : 10 + }, + "dfrbp" : { + "description" : "Delay flop, inverted reset, complementary outputs.", + "doc_name": "DFFRRx", + "doc_ref" : 11 + }, + "dlhq" : { + "description" : "Delay latch, non-inverted enable, single output.", + "doc_name": "DLHQ", + "doc_ref" : 12 + }, + "dlhr" : { + "description" : "Delay latch, inverted reset, non-inverted enable, complementary outputs.", + "doc_name": "DLHR", + "doc_ref" : 14 + }, + "dlhrq" : { + "description" : "Delay latch, inverted reset, non-inverted enable, single output.", + "doc_name": "DLHRQ", + "doc_ref" : 13 + }, + "dllr" : { + "description" : "Delay latch, inverted reset, inverted enable, complementary outputs.", + "doc_name": "DLLR", + "doc_ref" : 16 + }, + "dllrq" : { + "description" : "Delay latch, inverted reset, inverted enable, single output.", + "doc_name": "DLLRQ", + "doc_ref" : 15 + }, + "dlygate4sd1" : { + "description" : "Delay Buffer 4-stage ... length inner stage gates.", + "doc_name": "DLY1", + "doc_ref" : 17 + }, + "dlygate4sd2" : { + "description" : "Delay Buffer 4-stage ... length inner stage gates.", + "doc_name": "DLY2", + "doc_ref" : 18 + }, + "dlygate4sd3" : { + "description" : "Delay Buffer 4-stage ... length inner stage gates.", + "doc_name": "DLY4", + "doc_ref" : 19 + }, + "ebufn" : { + "description" : "Tri-state buffer, negative enable.", + "doc_name": "BTLx", + "doc_ref" : 8 + }, + "einvn" : { + "description" : "Tri-state inverter, negative enable.", + "doc_name": "EINVINx, ITL", + "doc_ref" : 20 + }, + "fill" : { + "description" : "Fill cell.", + "doc_name": "FILLx", + "doc_ref" : 21 + }, + "inv" : { + "description" : "Inverter.", + "doc_name": "INx", + "doc_ref" : 23 + }, + "lgcp" : { + "description" : "Clock gate.", + "doc_name": "GCLK", + "doc_ref" : 22 + }, + "mux2" : { + "description" : "2-input multiplexer.", + "doc_name": "MUX2x", + "doc_ref" : 26 + }, + "mux4" : { + "description" : "4-input multiplexer.", + "doc_name": "MUX4", + "doc_ref" : 27 + }, + "nand2" : { + "description" : "2-input NAND.", + "doc_name": "NAND2x", + "doc_ref" : 30 + }, + "nand2b" : { + "description" : "2-input NAND, first input inverted.", + "doc_name": "NAND2B1, NAND2B2", + "doc_ref" : 28 + }, + "nand3" : { + "description" : "3-input NAND.", + "doc_name": "NAND3", + "doc_ref" : 32 + }, + "nand3b" : { + "description" : "3-input NAND, first input inverted.", + "doc_name": "NAND3B1", + "doc_ref" : 31 + }, + "nand4" : { + "description" : "4-input NAND.", + "doc_name": "NAND4", + "doc_ref" : 33 + }, + "nor2" : { + "description" : "2-input NOR.", + "doc_name": "NOR2x", + "doc_ref" : 35 + }, + "nor2b" : { + "description" : "2-input NOR, first input inverted.", + "doc_name": "NOR2Bx", + "doc_ref" : 34 + }, + "nor3" : { + "description" : "3-input NOR.", + "doc_name": "NOR3x", + "doc_ref" : 36 + }, + "nor4" : { + "description" : "4-input NOR.", + "doc_name": "NOR4x", + "doc_ref" : 37 + }, + "o21ai" : { + "description" : "2-input OR into first input of 2-input NAND.", + "doc_name": "O21AI", + "doc_ref" : 39 + }, + "or2" : { + "description" : "2-input OR.", + "doc_name": "OR2x", + "doc_ref" : 40 + }, + "or3" : { + "description" : "3-input OR.", + "doc_name": "OR3x", + "doc_ref" : 41 + }, + "or4" : { + "description" : "4-input OR.", + "doc_name": "OR4x", + "doc_ref" : 42 + }, + "sdfbbp" : { + "description" : "Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.", + "doc_name": "SDFRRS", + "doc_ref" : 43 + }, + "sighold" : { + "description" : "Cross-coupled inverters.", + "doc_name": "KEEPSTATE", + "doc_ref" : 25 + }, + "slgcp" : { + "description" : "Scan gated clock.", + "doc_name": "SGCLK", + "doc_ref" : 44 + }, + "tiehi" : { + "description" : "Constant high output.", + "doc_name": "TIE1", + "doc_ref" : 46 + }, + "tielo" : { + "description" : "Constant low output.", + "doc_name": "TIE0", + "doc_ref" : 45 + }, + "xnor2" : { + "description" : "2-input exclusive NOR.", + "doc_name": "XNOR2_1", + "doc_ref" : 47 + }, + "xor2" : { + "description" : "2-input exclusive OR.", + "doc_name": "XOR2_1", + "doc_ref" : 48 + } +} diff --git a/ihp/constraint.sdc b/ihp/constraint.sdc new file mode 100644 index 0000000..f9d362b --- /dev/null +++ b/ihp/constraint.sdc @@ -0,0 +1,13 @@ +set clk_name core_clock +set clk_port_name clk +set clk_period 20 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_port_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/ihp/def/tt_block_1x1.def b/ihp/def/tt_block_1x1.def new file mode 100644 index 0000000..ff86861 --- /dev/null +++ b/ihp/def/tt_block_1x1.def @@ -0,0 +1,285 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 212160 154980 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 430 BY 1 STEP 480 0 ; +TRACKS X 480 DO 441 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 504 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 441 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 504 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 441 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 93 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 53 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 154480 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 154480 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 154480 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 154480 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 154480 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 154480 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 154480 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 154480 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 154480 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 154480 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 154480 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 154480 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 154480 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 154480 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 154480 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 154480 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 154480 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 154480 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 154480 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 154480 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 154480 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 154480 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 154480 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 154480 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 154480 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 154480 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 154480 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 154480 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 154480 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 154480 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 154480 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 154480 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 154480 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 154480 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 154480 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 154480 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 154480 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 154480 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 154480 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 154480 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 154480 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 154480 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 154480 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_1x2.def b/ihp/def/tt_block_1x2.def new file mode 100644 index 0000000..db1d9e2 --- /dev/null +++ b/ihp/def/tt_block_1x2.def @@ -0,0 +1,327 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 212160 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 430 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 430 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 430 BY 1 STEP 480 0 ; +TRACKS X 480 DO 441 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 504 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 441 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 504 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 441 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 93 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 53 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_2x1.def b/ihp/def/tt_block_2x1.def new file mode 100644 index 0000000..47a8072 --- /dev/null +++ b/ihp/def/tt_block_2x1.def @@ -0,0 +1,285 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 427200 154980 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 878 BY 1 STEP 480 0 ; +TRACKS X 480 DO 889 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 1016 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 889 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 1016 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 889 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 187 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 107 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 154480 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 154480 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 154480 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 154480 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 154480 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 154480 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 154480 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 154480 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 154480 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 154480 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 154480 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 154480 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 154480 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 154480 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 154480 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 154480 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 154480 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 154480 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 154480 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 154480 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 154480 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 154480 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 154480 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 154480 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 154480 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 154480 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 154480 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 154480 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 154480 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 154480 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 154480 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 154480 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 154480 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 154480 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 154480 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 154480 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 154480 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 154480 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 154480 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 154480 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 154480 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 154480 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 154480 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_2x2.def b/ihp/def/tt_block_2x2.def new file mode 100644 index 0000000..133c92d --- /dev/null +++ b/ihp/def/tt_block_2x2.def @@ -0,0 +1,327 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 427200 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 878 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 878 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 878 BY 1 STEP 480 0 ; +TRACKS X 480 DO 889 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 1016 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 889 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 1016 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 889 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 187 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 107 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_3x1.def b/ihp/def/tt_block_3x1.def new file mode 100644 index 0000000..1a72d05 --- /dev/null +++ b/ihp/def/tt_block_3x1.def @@ -0,0 +1,285 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 642240 154980 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 1326 BY 1 STEP 480 0 ; +TRACKS X 480 DO 1337 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 1528 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 1337 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 1528 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 1337 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 281 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 160 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 154480 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 154480 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 154480 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 154480 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 154480 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 154480 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 154480 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 154480 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 154480 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 154480 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 154480 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 154480 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 154480 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 154480 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 154480 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 154480 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 154480 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 154480 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 154480 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 154480 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 154480 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 154480 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 154480 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 154480 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 154480 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 154480 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 154480 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 154480 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 154480 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 154480 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 154480 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 154480 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 154480 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 154480 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 154480 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 154480 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 154480 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 154480 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 154480 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 154480 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 154480 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 154480 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 154480 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_3x2.def b/ihp/def/tt_block_3x2.def new file mode 100644 index 0000000..afb06db --- /dev/null +++ b/ihp/def/tt_block_3x2.def @@ -0,0 +1,327 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 642240 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 1326 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 1326 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 1326 BY 1 STEP 480 0 ; +TRACKS X 480 DO 1337 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 1528 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 1337 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 1528 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 1337 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 281 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 160 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_4x1.def b/ihp/def/tt_block_4x1.def new file mode 100644 index 0000000..5a09a4a --- /dev/null +++ b/ihp/def/tt_block_4x1.def @@ -0,0 +1,285 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 857280 154980 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 1774 BY 1 STEP 480 0 ; +TRACKS X 480 DO 1785 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 2040 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 1785 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 2040 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 1785 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 376 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 214 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 154480 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 154480 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 154480 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 154480 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 154480 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 154480 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 154480 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 154480 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 154480 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 154480 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 154480 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 154480 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 154480 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 154480 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 154480 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 154480 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 154480 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 154480 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 154480 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 154480 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 154480 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 154480 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 154480 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 154480 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 154480 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 154480 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 154480 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 154480 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 154480 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 154480 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 154480 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 154480 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 154480 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 154480 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 154480 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 154480 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 154480 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 154480 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 154480 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 154480 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 154480 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 154480 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 154480 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_4x2.def b/ihp/def/tt_block_4x2.def new file mode 100644 index 0000000..72818e5 --- /dev/null +++ b/ihp/def/tt_block_4x2.def @@ -0,0 +1,327 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 857280 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 1774 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 1774 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 1774 BY 1 STEP 480 0 ; +TRACKS X 480 DO 1785 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 2040 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 1785 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 2040 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 1785 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 376 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 214 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_6x1.def b/ihp/def/tt_block_6x1.def new file mode 100644 index 0000000..88eb66f --- /dev/null +++ b/ihp/def/tt_block_6x1.def @@ -0,0 +1,285 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1287360 154980 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 2670 BY 1 STEP 480 0 ; +TRACKS X 480 DO 2681 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 3064 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 2681 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 3064 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 2681 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 564 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 154480 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 154480 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 154480 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 154480 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 154480 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 154480 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 154480 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 154480 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 154480 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 154480 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 154480 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 154480 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 154480 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 154480 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 154480 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 154480 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 154480 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 154480 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 154480 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 154480 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 154480 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 154480 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 154480 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 154480 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 154480 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 154480 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 154480 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 154480 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 154480 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 154480 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 154480 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 154480 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 154480 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 154480 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 154480 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 154480 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 154480 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 154480 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 154480 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 154480 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 154480 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 154480 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 154480 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_6x2.def b/ihp/def/tt_block_6x2.def new file mode 100644 index 0000000..51d139d --- /dev/null +++ b/ihp/def/tt_block_6x2.def @@ -0,0 +1,327 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1287360 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 2670 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 2670 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 2670 BY 1 STEP 480 0 ; +TRACKS X 480 DO 2681 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 3064 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 2681 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 3064 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 2681 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 564 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_8x1.def b/ihp/def/tt_block_8x1.def new file mode 100644 index 0000000..e49f5ea --- /dev/null +++ b/ihp/def/tt_block_8x1.def @@ -0,0 +1,285 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1717440 154980 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 3566 BY 1 STEP 480 0 ; +TRACKS X 480 DO 3577 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 4088 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 3577 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 4088 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 3577 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 753 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 429 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 154480 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 154480 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 154480 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 154480 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 154480 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 154480 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 154480 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 154480 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 154480 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 154480 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 154480 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 154480 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 154480 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 154480 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 154480 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 154480 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 154480 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 154480 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 154480 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 154480 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 154480 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 154480 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 154480 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 154480 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 154480 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 154480 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 154480 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 154480 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 154480 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 154480 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 154480 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 154480 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 154480 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 154480 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 154480 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 154480 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 154480 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 154480 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 154480 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 154480 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 154480 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 154480 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 154480 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/def/tt_block_8x2.def b/ihp/def/tt_block_8x2.def new file mode 100644 index 0000000..6e9507b --- /dev/null +++ b/ihp/def/tt_block_8x2.def @@ -0,0 +1,327 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN tt_um_template ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 1717440 313740 ) ; +ROW ROW_0 CoreSite 2880 3780 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_1 CoreSite 2880 7560 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_2 CoreSite 2880 11340 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_3 CoreSite 2880 15120 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_4 CoreSite 2880 18900 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_5 CoreSite 2880 22680 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_6 CoreSite 2880 26460 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_7 CoreSite 2880 30240 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_8 CoreSite 2880 34020 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_9 CoreSite 2880 37800 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_10 CoreSite 2880 41580 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_11 CoreSite 2880 45360 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_12 CoreSite 2880 49140 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_13 CoreSite 2880 52920 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_14 CoreSite 2880 56700 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_15 CoreSite 2880 60480 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_16 CoreSite 2880 64260 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_17 CoreSite 2880 68040 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_18 CoreSite 2880 71820 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_19 CoreSite 2880 75600 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_20 CoreSite 2880 79380 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_21 CoreSite 2880 83160 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_22 CoreSite 2880 86940 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_23 CoreSite 2880 90720 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_24 CoreSite 2880 94500 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_25 CoreSite 2880 98280 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_26 CoreSite 2880 102060 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_27 CoreSite 2880 105840 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_28 CoreSite 2880 109620 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_29 CoreSite 2880 113400 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_30 CoreSite 2880 117180 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_31 CoreSite 2880 120960 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_32 CoreSite 2880 124740 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_33 CoreSite 2880 128520 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_34 CoreSite 2880 132300 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_35 CoreSite 2880 136080 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_36 CoreSite 2880 139860 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_37 CoreSite 2880 143640 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_38 CoreSite 2880 147420 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_39 CoreSite 2880 151200 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_40 CoreSite 2880 154980 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_41 CoreSite 2880 158760 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_42 CoreSite 2880 162540 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_43 CoreSite 2880 166320 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_44 CoreSite 2880 170100 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_45 CoreSite 2880 173880 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_46 CoreSite 2880 177660 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_47 CoreSite 2880 181440 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_48 CoreSite 2880 185220 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_49 CoreSite 2880 189000 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_50 CoreSite 2880 192780 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_51 CoreSite 2880 196560 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_52 CoreSite 2880 200340 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_53 CoreSite 2880 204120 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_54 CoreSite 2880 207900 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_55 CoreSite 2880 211680 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_56 CoreSite 2880 215460 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_57 CoreSite 2880 219240 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_58 CoreSite 2880 223020 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_59 CoreSite 2880 226800 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_60 CoreSite 2880 230580 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_61 CoreSite 2880 234360 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_62 CoreSite 2880 238140 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_63 CoreSite 2880 241920 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_64 CoreSite 2880 245700 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_65 CoreSite 2880 249480 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_66 CoreSite 2880 253260 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_67 CoreSite 2880 257040 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_68 CoreSite 2880 260820 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_69 CoreSite 2880 264600 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_70 CoreSite 2880 268380 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_71 CoreSite 2880 272160 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_72 CoreSite 2880 275940 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_73 CoreSite 2880 279720 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_74 CoreSite 2880 283500 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_75 CoreSite 2880 287280 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_76 CoreSite 2880 291060 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_77 CoreSite 2880 294840 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_78 CoreSite 2880 298620 N DO 3566 BY 1 STEP 480 0 ; +ROW ROW_79 CoreSite 2880 302400 FS DO 3566 BY 1 STEP 480 0 ; +ROW ROW_80 CoreSite 2880 306180 N DO 3566 BY 1 STEP 480 0 ; +TRACKS X 480 DO 3577 STEP 480 LAYER Metal1 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ; +TRACKS X 420 DO 4088 STEP 420 LAYER Metal2 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ; +TRACKS X 480 DO 3577 STEP 480 LAYER Metal3 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ; +TRACKS X 420 DO 4088 STEP 420 LAYER Metal4 ; +TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ; +TRACKS X 480 DO 3577 STEP 480 LAYER Metal5 ; +TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ; +TRACKS X 1460 DO 753 STEP 2280 LAYER TopMetal1 ; +TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ; +TRACKS X 2000 DO 429 STEP 4000 LAYER TopMetal2 ; +TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ; +COMPONENTS 0 ; +END COMPONENTS +PINS 43 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 198720 313240 ) N ; + - ena + NET ena + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 202560 313240 ) N ; + - rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 194880 313240 ) N ; + - ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 191040 313240 ) N ; + - ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 187200 313240 ) N ; + - ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 183360 313240 ) N ; + - ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 179520 313240 ) N ; + - ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 175680 313240 ) N ; + - ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 171840 313240 ) N ; + - ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 168000 313240 ) N ; + - ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 164160 313240 ) N ; + - uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 160320 313240 ) N ; + - uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 156480 313240 ) N ; + - uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 152640 313240 ) N ; + - uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 148800 313240 ) N ; + - uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 144960 313240 ) N ; + - uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 141120 313240 ) N ; + - uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 137280 313240 ) N ; + - uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 133440 313240 ) N ; + - uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 68160 313240 ) N ; + - uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 64320 313240 ) N ; + - uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 60480 313240 ) N ; + - uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 56640 313240 ) N ; + - uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 52800 313240 ) N ; + - uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 48960 313240 ) N ; + - uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 45120 313240 ) N ; + - uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 41280 313240 ) N ; + - uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 98880 313240 ) N ; + - uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 95040 313240 ) N ; + - uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 91200 313240 ) N ; + - uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 87360 313240 ) N ; + - uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 83520 313240 ) N ; + - uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 79680 313240 ) N ; + - uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 75840 313240 ) N ; + - uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 72000 313240 ) N ; + - uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 129600 313240 ) N ; + - uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 125760 313240 ) N ; + - uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 121920 313240 ) N ; + - uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 118080 313240 ) N ; + - uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 114240 313240 ) N ; + - uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 110400 313240 ) N ; + - uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 106560 313240 ) N ; + - uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER Metal5 ( -150 -500 ) ( 150 500 ) + + PLACED ( 102720 313240 ) N ; +END PINS +SPECIALNETS 2 ; + - VGND + USE GROUND ; + - VPWR + USE POWER ; +END SPECIALNETS +NETS 43 ; + - clk ( PIN clk ) + USE SIGNAL ; + - ena ( PIN ena ) + USE SIGNAL ; + - rst_n ( PIN rst_n ) + USE SIGNAL ; + - ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ; + - ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ; + - ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ; + - ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ; + - ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ; + - ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ; + - ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ; + - ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ; + - uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ; + - uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ; + - uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ; + - uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ; + - uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ; + - uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ; + - uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ; + - uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ; + - uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ; + - uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ; + - uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ; + - uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ; + - uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ; + - uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ; + - uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ; + - uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ; + - uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ; + - uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ; + - uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ; + - uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ; + - uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ; + - uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ; + - uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ; + - uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ; + - uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ; + - uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ; + - uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ; + - uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ; + - uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ; + - uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ; + - uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ; + - uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/ihp/pdn.tcl b/ihp/pdn.tcl new file mode 100644 index 0000000..8426d5e --- /dev/null +++ b/ihp/pdn.tcl @@ -0,0 +1,18 @@ +# global connections +add_global_connection -net {VDD} -pin_pattern {^VDD$} -power +add_global_connection -net {VDD} -pin_pattern {^VDDPE$} +add_global_connection -net {VDD} -pin_pattern {^VDDCE$} +add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground +add_global_connection -net {VSS} -pin_pattern {^VSSE$} +global_connect + +# voltage domains +set_voltage_domain -name {CORE} -power {VDD} -ground {VSS} + +# standard cell grid +define_pdn_grid -name {grid} -voltage_domains {CORE} +add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -extend_to_boundary -followpins +add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_boundary +add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_boundary +add_pdn_connect -grid {grid} -layers {Metal1 Metal5} +add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1} diff --git a/ihp/tile_sizes.yaml b/ihp/tile_sizes.yaml new file mode 100644 index 0000000..7995eab --- /dev/null +++ b/ihp/tile_sizes.yaml @@ -0,0 +1,12 @@ +1x1: "0 0 212.16 154.98" +1x2: "0 0 212.16 313.74" +2x1: "0 0 427.20 154.98" +2x2: "0 0 427.20 313.74" +3x1: "0 0 642.24 154.98" +3x2: "0 0 642.24 313.74" +4x1: "0 0 857.28 154.98" +4x2: "0 0 857.28 313.74" +6x1: "0 0 1287.36 154.98" +6x2: "0 0 1287.36 313.74" +8x1: "0 0 1717.44 154.98" +8x2: "0 0 1717.44 313.74" diff --git a/project.py b/project.py index 6e0acaa..4445bb1 100644 --- a/project.py +++ b/project.py @@ -17,16 +17,21 @@ import yaml from git.repo import Repo import git_utils -from cells import Cell, load_cells +from cells import Sky130Cell, load_ihp_cells, load_sky130_cells from config_utils import read_config, write_config from markdown_utils import limit_markdown_headings from project_info import ProjectInfo, ProjectYamlError -_CELL_URL_FMT = "https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/cells/{name}/README.html" +_SKY130_CELL_URL_FMT = "https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/cells/{name}/README.html" +_IHP_CELL_URL_FMT = "https://raw.githubusercontent.com/IHP-GmbH/IHP-Open-PDK/refs/heads/main/ihp-sg13g2/libs.ref/sg13g2_stdcell/doc/sg13g2_stdcell_typ_1p50V_25C.pdf#{ref}" -def _cell_url(cell_name): - return _CELL_URL_FMT.format(name=cell_name) +def _sky130_cell_url(cell_name): + return _SKY130_CELL_URL_FMT.format(name=cell_name) + + +def _ihp_cell_url(doc_ref): + return _IHP_CELL_URL_FMT.format(ref=doc_ref) PINOUT_KEYS = [ @@ -65,6 +70,7 @@ with open(os.path.join(os.path.dirname(__file__), "tile_sizes.yaml"), "r") as st class Args: openlane2: bool + orfs: bool print_cell_summary: bool print_cell_category: bool @@ -87,7 +93,7 @@ class Project: self.git_url = git_url self.args = args self.index = index - self.local_dir = local_dir + self.local_dir = os.path.realpath(local_dir) self.is_user_project = is_user_project self.src_dir = ( os.path.join(self.local_dir, "src") @@ -130,12 +136,16 @@ class Project: def load_metrics(self): try: if self.is_user_project: + orfs = self.args.orfs openlane2 = self.args.openlane2 else: commit_data = json.load(open("commit_id.json")) - openlane2 = commit_data["openlane_version"].startswith("OpenLane2") + orfs = "orfs_version" in commit_data + openlane2 = commit_data.get("openlane_version", "").startswith( + "OpenLane2" + ) with open(self.get_metrics_path()) as fh: - if openlane2: + if orfs or openlane2: self.metrics = dict(csv.reader(fh)) else: self.metrics = next(csv.DictReader(fh)) @@ -355,7 +365,12 @@ class Project: # metrics def get_metrics_path(self): if self.is_user_project: - if self.args.openlane2: + if self.args.orfs: + return os.path.join( + self.local_dir, + "runs/ihp/results/ihp-sg13g2/tt-submission/base/metrics.csv", + ) + elif self.args.openlane2: return os.path.join(self.local_dir, "runs/wokwi/final/metrics.csv") else: return os.path.join(self.local_dir, "runs/wokwi/reports/metrics.csv") @@ -364,6 +379,11 @@ class Project: def get_gl_path(self): if self.is_user_project: + if self.args.orfs: + return os.path.join( + self.local_dir, + "runs/ihp/results/ihp-sg13g2/tt-submission/base/6_final.v", + ) if self.args.openlane2: return glob.glob( os.path.join(self.local_dir, "runs/wokwi/final/nl/*.nl.v") @@ -475,13 +495,24 @@ class Project: self.check_ports() logging.info("creating include file") tiles = self.info.tiles - die_area = tile_sizes[tiles] - config = { - "DESIGN_NAME": self.info.top_module, - "VERILOG_FILES": [f"dir::{src}" for src in self.sources], - "DIE_AREA": die_area, - "FP_DEF_TEMPLATE": f"dir::../tt/def/tt_block_{tiles}_pg.def", - } + if self.args.orfs: + config = { + "DESIGN_NICKNAME": "tt-submission", + "DESIGN_NAME": self.info.top_module, + "PLATFORM": "ihp-sg13g2", + "VERILOG_FILES": [f"dir::{src}" for src in self.sources], + "FLOORPLAN_DEF": f"dir::../tt/ihp/def/tt_block_{tiles}.def", + "SDC_FILE": f"dir::../tt/ihp/constraint.sdc", + "PDN_TCL": f"dir::../tt/ihp/pdn.tcl", + } + else: + die_area = tile_sizes[tiles] + config = { + "DESIGN_NAME": self.info.top_module, + "VERILOG_FILES": [f"dir::{src}" for src in self.sources], + "DIE_AREA": die_area, + "FP_DEF_TEMPLATE": f"dir::../tt/def/tt_block_{tiles}_pg.def", + } write_config(config, os.path.join(self.src_dir, "user_config"), ("json",)) def golden_harden(self): @@ -501,28 +532,63 @@ class Project: config = read_config("src/config", ("json", "tcl")) user_config = read_config("src/user_config", ("json",)) config.update(user_config) - write_config(config, "src/config_merged", ("json",)) + if self.args.orfs: + write_config(config, "src/config_merged", ("mk",)) + else: + write_config(config, "src/config_merged", ("json",)) - if self.args.openlane2: + if self.args.orfs: + shutil.rmtree("runs/ihp", ignore_errors=True) + os.makedirs("runs/ihp", exist_ok=True) + harden_cmd = f"make -B -C $ORFS_ROOT/flow all generate_abstract" + env = os.environ.copy() + if "ORFS_ROOT" not in env: + env["ORFS_ROOT"] = os.path.join(self.local_dir, "OpenROAD-flow-scripts") + if "OPENROAD_EXE" not in env: + openroad_exe = shutil.which("openroad") + if openroad_exe is None: + raise FileNotFoundError("OpenROAD executable not found") + env["OPENROAD_EXE"] = openroad_exe + if "YOSYS_EXE" not in env: + yosys_exe = shutil.which("yosys") + if yosys_exe is None: + raise FileNotFoundError("Yosys executable not found") + env["YOSYS_EXE"] = yosys_exe + if "IHP_PDK_ROOT" not in env: + env["IHP_PDK_ROOT"] = os.path.join(self.local_dir, "IHP-Open-PDK") + if "KLAYOUT_HOME" not in env: + env["KLAYOUT_HOME"] = os.path.join( + env["IHP_PDK_ROOT"], "ihp-sg13g2/libs.tech/klayout" + ) + env["WORK_HOME"] = os.path.join(self.local_dir, "runs/ihp") + env["DESIGN_HOME"] = self.src_dir + env["DESIGN_CONFIG"] = os.path.join(self.src_dir, "config_merged.mk") + elif self.args.openlane2: shutil.rmtree("runs/wokwi", ignore_errors=True) os.makedirs("runs/wokwi", exist_ok=True) arg_progress = "--hide-progress-bar" if "CI" in os.environ else "" arg_pdk_root = '--pdk-root "$PDK_ROOT"' if "PDK_ROOT" in os.environ else "" harden_cmd = f"python -m openlane {arg_pdk_root} --docker-no-tty --dockerized --run-tag wokwi --force-run-dir runs/wokwi {arg_progress} src/config_merged.json" + env = os.environ.copy() else: # requires PDK, PDK_ROOT, OPENLANE_ROOT & OPENLANE_IMAGE_NAME to be set in local environment harden_cmd = "docker run --rm -v $OPENLANE_ROOT:/openlane -v $PDK_ROOT:$PDK_ROOT -v $(pwd):/work -e PDK=$PDK -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) $OPENLANE_IMAGE_NAME ./flow.tcl -overwrite -design /work/src -run_path /work/runs -config_file /work/src/config_merged.json -tag wokwi" + env = os.environ.copy() logging.debug(harden_cmd) - env = os.environ.copy() p = subprocess.run(harden_cmd, shell=True, env=env) if p.returncode != 0: logging.error("harden failed") exit(1) # Write commit information - commit_id_json_path = "runs/wokwi/results/final/commit_id.json" - if self.args.openlane2: + if self.args.orfs: + commit_id_json_path = ( + "runs/ihp/results/ihp-sg13g2/tt-submission/base/commit_id.json" + ) + elif self.args.openlane2: commit_id_json_path = "runs/wokwi/final/commit_id.json" + else: + commit_id_json_path = "runs/wokwi/results/final/commit_id.json" with open(os.path.join(self.local_dir, commit_id_json_path), "w") as f: json.dump( { @@ -536,7 +602,47 @@ class Project: ) f.write("\n") - if self.args.openlane2: + # Collect metrics + if self.args.orfs: + metrics = {} + metrics_inputs = glob.glob( + os.path.join( + self.local_dir, "runs/ihp/logs/ihp-sg13g2/tt-submission/base/*.json" + ) + ) + for metrics_input in metrics_inputs: + with open(metrics_input) as mf: + metrics.update(json.load(mf)) + metrics_output = ( + "runs/ihp/results/ihp-sg13g2/tt-submission/base/metrics.csv" + ) + with open(metrics_output, "w") as mf: + wr = csv.writer(mf) + wr.writerow(("Metric", "Value")) + wr.writerows(metrics.items()) + + if self.args.orfs: + tool_queries = [ + ("yosys", "shell", "yosys -V"), + ("openroad", "shell", "openroad -version"), + ("klayout", "shell", "klayout -v"), + ("orfs", "repo", env["ORFS_ROOT"]), + ("ihp_pdk", "repo", env["IHP_PDK_ROOT"]), + ] + tool_versions = {} + for tool_name, query_type, query_param in tool_queries: + if query_type == "shell": + tool_versions[tool_name] = subprocess.run( + query_param, shell=True, capture_output=True, text=True + ).stdout.strip() + elif query_type == "repo": + tool_versions[tool_name] = ( + Repo(os.path.join(self.local_dir, query_param)).commit().hexsha + ) + with open("runs/ihp/tool_versions.json", "w") as f: + json.dump(tool_versions, f, indent=2) + + elif self.args.openlane2: resolved_json_path = "runs/wokwi/resolved.json" config = json.load(open(os.path.join(self.local_dir, resolved_json_path))) openlane_version = config["meta"]["openlane_version"] @@ -676,6 +782,11 @@ class Project: def get_final_gds_top_cells(self): if "GDS_PATH" in os.environ: gds_path = os.environ["GDS_PATH"] + elif self.args.orfs: + gds_path = os.path.join( + self.local_dir, + "runs/ihp/results/ihp-sg13g2/tt-submission/base/6_final.gds", + ) elif self.args.openlane2: gds_path = glob.glob( os.path.join(self.local_dir, "runs/wokwi/final/gds/*.gds") @@ -713,9 +824,20 @@ class Project: (70, 5), # 70/5 - met3.label (71, 5), # 71/5 - met4.label ] - top_cells.filter(sky130_label_layers) + ihp_label_layers = [ + (8, 1), # 8/1 - Metal1.label + (8, 25), # 8/25 - Metal1.text + (67, 25), # 67/25 - Metal5.text + (126, 25), # 126/25 - TopMetal1.text + ] + if self.args.orfs: + label_layers = ihp_label_layers + else: + label_layers = sky130_label_layers + + top_cells.filter(label_layers) for subcell in top_cells.dependencies(True): - subcell.filter(sky130_label_layers) + subcell.filter(label_layers) svg = "gds_render_preview.svg" logging.info("Rendering SVG without text label layers: {}".format(svg)) top_cells.write_svg(svg, pad=0) @@ -756,9 +878,21 @@ class Project: # Less important, but keep for now: # (69,20), # 69/20 - met2.drawing ] - top_cells.filter(sky130_buried_layers) + ihp_buried_layers = [ + (6, 0), # 6/0 - Cont.drawing + (8, 2), # 8/2 - Metal1.pin + (19, 0), # 19/0 - Via1.drawing + (51, 0), # 51/0 - HeatTrans.drawing + (189, 4), # 189/4 - prBoundary.boundary + ] + if self.args.orfs: + buried_layers = ihp_buried_layers + else: + buried_layers = sky130_buried_layers + + top_cells.filter(buried_layers) for subcell in top_cells.dependencies(True): - subcell.filter(sky130_buried_layers) + subcell.filter(buried_layers) svg_alt = "gds_render_preview_alt.svg" logging.info("Rendering SVG with more layers removed: {}".format(svg_alt)) top_cells.write_svg(svg_alt, pad=0) @@ -814,10 +948,13 @@ class Project: def print_warnings(self): warnings: typing.List[str] = [] - synth_log = "runs/wokwi/logs/synthesis/1-synthesis.log" - if self.args.openlane2: + if self.args.orfs: + synth_log = "runs/ihp/logs/ihp-sg13g2/tt-submission/base/1_1_yosys.log" + elif self.args.openlane2: synth_log_glob = "runs/wokwi/*-yosys-synthesis/yosys-synthesis.log" synth_log = glob.glob(os.path.join(self.local_dir, synth_log_glob))[0] + else: + synth_log = "runs/wokwi/logs/synthesis/1-synthesis.log" with open(os.path.join(self.local_dir, synth_log)) as f: for line in f.readlines(): if line.startswith("Warning:"): @@ -825,19 +962,24 @@ class Project: if "WIDTHLABEL" not in line: warnings.append(line.strip()) - sta_report_glob = ( - "runs/wokwi/reports/signoff/*-sta-rcx_nom/multi_corner_sta.checks.rpt" - ) - - if self.args.openlane2: - sta_report_glob = ( - "runs/wokwi/*-openroad-stapostpnr/nom_tt_025C_1v80/checks.rpt" - ) - sta_report = glob.glob(os.path.join(self.local_dir, sta_report_glob))[0] - with open(os.path.join(self.local_dir, sta_report)) as f: - for line in f.readlines(): - if line.startswith("Warning:") and "clock" in line: - warnings.append(line.strip()) + if self.args.orfs: + report = "runs/ihp/logs/ihp-sg13g2/tt-submission/base/6_report.log" + with open(os.path.join(self.local_dir, report)) as f: + for line in f.readlines(): + if line.startswith("Warning:"): + warnings.append(line.strip()) + else: + if self.args.openlane2: + sta_report_glob = ( + "runs/wokwi/*-openroad-stapostpnr/nom_tt_025C_1v80/checks.rpt" + ) + else: + sta_report_glob = "runs/wokwi/reports/signoff/*-sta-rcx_nom/multi_corner_sta.checks.rpt" + sta_report = glob.glob(os.path.join(self.local_dir, sta_report_glob))[0] + with open(os.path.join(self.local_dir, sta_report)) as f: + for line in f.readlines(): + if line.startswith("Warning:") and "clock" in line: + warnings.append(line.strip()) if len(warnings): print("# Synthesis warnings") @@ -846,18 +988,26 @@ class Project: print(f"* {warning}") def print_stats(self): - if self.args.openlane2: - # openlane2 doesn't have the same util% in its metrics as openlane1 - util_glob = ( - "runs/wokwi/*-openroad-globalplacement/openroad-globalplacement.log" - ) - util_log = glob.glob(os.path.join(self.local_dir, util_glob))[0] + if self.args.orfs or self.args.openlane2: + # ORFS & openlane2 don't have the same util% in its metrics as openlane1 + if self.args.orfs: + util_log = ( + "runs/ihp/logs/ihp-sg13g2/tt-submission/base/3_3_place_gp.log" + ) + else: + util_glob = ( + "runs/wokwi/*-openroad-globalplacement/openroad-globalplacement.log" + ) + util_log = glob.glob(os.path.join(self.local_dir, util_glob))[0] util_label = "[INFO GPL-0019] Util:" util_line = next( line for line in open(util_log) if line.startswith(util_label) ) util = util_line.removeprefix(util_label).strip() - wire_length = self.metrics["route__wirelength"] + if self.args.orfs: + wire_length = self.metrics["detailedroute__route__wirelength"] + else: + wire_length = self.metrics["route__wirelength"] else: util = self.metrics["OpenDP_Util"] wire_length = self.metrics["wire_length"] @@ -875,10 +1025,23 @@ class Project: Categories = typing.TypedDict( "Categories", {"categories": typing.List[str], "map": typing.Dict[str, int]} ) - with open(os.path.join(SCRIPT_DIR, "categories.json")) as fh: + if self.args.orfs: + categories_file = "ihp/categories.json" + else: + categories_file = "categories.json" + with open(os.path.join(SCRIPT_DIR, categories_file)) as fh: categories: Categories = json.load(fh) - defs = load_cells() + if self.args.orfs: + ihp_defs = load_ihp_cells() + else: + sky130_defs = load_sky130_cells() + + def _cell_url(name): + if self.args.orfs: + return _ihp_cell_url(ihp_defs[name]["doc_ref"]) + else: + return _sky130_cell_url(name) # print all used cells, sorted by frequency total = 0 @@ -893,9 +1056,11 @@ class Project: if count > 0: total += count cell_link = _cell_url(name) - print( - f'| [{name}]({cell_link}) | {defs[name]["description"]} |{count} |' - ) + if self.args.orfs: + description = ihp_defs[name]["description"] + else: + description = sky130_defs[name]["description"] + print(f"| [{name}]({cell_link}) | {description} |{count} |") print(f"| | Total | {total} |") @@ -956,12 +1121,16 @@ class Project: total = 0 with open(self.get_gl_path()) as fh: for line in fh.readlines(): - m = re.search(r"sky130_(\S+)__(\S+)_(\d+)", line) + if self.args.orfs: + cell_re = r"sg13g2()_(\S+)_(\d+)" + else: + cell_re = r"sky130_(\S+)__(\S+)_(\d+)" + m = re.search(cell_re, line) if m is not None: total += 1 cell_lib = m.group(1) cell_name = m.group(2) - assert cell_lib in ["fd_sc_hd", "ef_sc_hd"] + assert cell_lib in ["fd_sc_hd", "ef_sc_hd", ""] try: cell_count[cell_name] += 1 except KeyError: @@ -973,10 +1142,10 @@ class Project: def create_defs(self): # replace this with a find json_files = glob.glob("sky130_fd_sc_hd/latest/cells/*/definition.json") - definitions: typing.Dict[str, Cell] = {} + definitions: typing.Dict[str, Sky130Cell] = {} for json_file in json_files: with open(json_file) as fh: - definition: Cell = json.load(fh) + definition: Sky130Cell = json.load(fh) definitions[definition["name"]] = definition with open("cells.json", "w") as fh: diff --git a/tt_tool.py b/tt_tool.py index 2c7df31..4664f4e 100755 --- a/tt_tool.py +++ b/tt_tool.py @@ -26,6 +26,13 @@ if __name__ == "__main__": const=True, default=False, ) + parser.add_argument( + "--orfs", + help="use ORFS", + action="store_const", + const=True, + default=False, + ) # reports & summaries parser.add_argument(